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19.8.2 Serial I/O (UART Mode)
19.8.1.1 Special Mode 1 (I
When generating start, stop and restart conditions, set the STSPSEL bit in the U2SMR4 register to "0"
and wait for more than half cycle of the transfer clock before setting each condition generate bit
(STAREQ, RSTAREQ and STPREQ) from "0" to "1".
19.8.1.2 Special Mode 2
If a low-level signal is applied to the P8
to "1" (three-phase output forcible cutoff by input on SD pin enabled), the P7
U1MAP bit in PACR register is "1") and CLK
19.8.1.3 Special Mode 4 (SIM Mode)
A transmit interrupt request is generated by setting the U2IRS bit in the U2C1 register to "1" (transmis-
sion complete) and U2ERE bit to "1" (error signal output) after reset. Therefore, when using SIM
mode, be sure to clear the IR bit to "0" (no interrupt request) after setting these bits.
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C bus Mode)
page 314
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_______ _____
/NMI/SD pin when the IVPCR1 bit in the TB2SC register is set
5
_____
pins go to a high-impedance state.
2
19. Usage Notes
/RTS
/TxD1(when the
3
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