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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
PLL control register 0
b7
b6
b5
b4
0
0 1
NOTES:
1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable).
2. When the PM21 bit in the PM2 register is "1" (clock modification disable), writing to this register has
no effect.
3. These three bits can only be modified when the PLC07 bit is set to "0" (PLL turned off). The value once
written to this bit cannot be modified.
4. Before setting this bit to "1" , set the CM07 bit to "0" (main clock), set the CM17 and CM16 bits to
"00
" (main clock undivided mode), and set the CM06 bit to "0" (CM16 and CM17 bits enable).
2
Figure 7.7. PLC0 Register
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
6
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
(1, 2)
b3
b2
b1
b0
Symbol
PLC0
Bit
symbol
PLL multiplying factor
PLC00
select bit
PLC01
PLC02
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
(b3)
Reserved bit
(b4)
Reserved bit
(b6-b5)
Operation enable bit
PLC07
page 44
f o
3
2
9
6
C
2 /
6
) T
Address
001C
16
Bit name
b2
b1b0
0 0 0:
(3)
0 0 1: Multiply by 2
0 1 0: Multiply by 4
0 1 1:
1 0 0:
1 0 1:
1 1 0:
1 1 1:
Must set to "1"
Must set to "0"
0: PLL Off
1: PLL On
(4)
7. Clock Generation Circuit
After reset
0001 X010
2
Function
Do not set
Do not set
RW
RW
RW
RW
RW
RW
RW
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