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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
6
19.9 A/D Converter
1. Set ADCON0 (except bit 6), ADCON1 and ADCON2 registers when A/D conversion is stopped (before
a trigger occurs).
2. When the VCUT bit in the ADCON1 register is changed from "0" (Vref not connected) to "1" (V
connected), start A/D conversion after waiting 1 µs or longer.
3. To prevent noise-induced device malfunction or latchup, as well as to reduce conversion errors, insert
capacitors between the AV
and the AV
pin. Similarly, insert a capacitor between the V
SS
example connection of each pin.
4. Make sure the port direction bits for those pins that are used as analog inputs are set to "0" (input
mode). Also, if the TGR bit in ADCON0 register is set to "1" (external trigger), make sure the port
direction bit for the AD
5. When using key input interrupts, do not use any of the four AN
input interrupt request is generated when the A/D input voltage goes low.)
6. The φ
frequency must be 10 MHz or less (12 MHz or less in M16C/26B). Without sample-and-hold
AD
function, limit the φ
frequency to 1MH
7. When changing an A/D operation mode, select analog input pin again in the CH2 to CH0 bits in the
ADCON0 register and the SCAN1 to SCAN0 bits in the ADCON1 register.
V
CC
AN
i
NOTES:
Figure 19.3. Use of capacitors to reduce noise
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
, V
, and analog input pins (AN
CC
REF
___________
pin is set to "0" (input mode).
TRG
frequency to 250kH
AD
or more.
Z
Microcomputer
V
AV
CC
C4
V
V
REF
SS
AV
AN
: AN
(i=0 to 7), AN
, and AN
i
24
1. C1 ≥ 0.47 µF, C2 ≥ 0.47 µF, C3 ≥ 100 pF, C4 ≥ 0.1 µF (reference)
2. Use thick and shortest possible wiring to connect capacitors.
page 315
f o
3
2
9
6
C
2 /
6
) T
CC
or more. With the sample and hold function, limit the φ
Z
CC
C2
C1
SS
C3
i
(i=0 to 2)
3i
(i=0 to 7), AN
, AN
i
24
pin and the V
pin. Figure 19.4 is an
SS
to AN
pins as analog inputs. (A key
4
7
V
CC
19. Usage Notes
REF
(i=0 to 2)) each
3i
AD
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