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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
Timer Bi register (i=0 to 2)(1)
(b15)
b7
NOTES:
1. The register must be accessed in 16 bit units.
2. The timer counts pulses from an external device or overflows or underflows of other timers.
3. When this mode is used combining delayed trigger mode 0, set the larger value than the value of the timer
B0 register to the timer B1 register.
Count start flag
b7
b6
b5
b4
b3
Clock prescaler reset flag
b7
b6
b5
b4
b3
Figure 12.2.3. TB0 to TB2 Registers, TABSR Register, CPSRF Register
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
6
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
(b8)
b0 b7
b0
Mode
Timer mode
Event counter
mode
Pulse period
modulation mode,
Pulse width
modulation mode
A/D trigger
mode (3)
Symbol
b2
b1
b0
TABSR
Bit symbol
TA0S
Timer A0 count start flag
TA1S
Timer A1 count start flag
TA2S
Timer A2 count start flag
TA3S
Timer A3 count start flag
TA4S
Timer A4 count start flag
TB0S
Timer B0 count start flag
TB1S
Timer B1 count start flag
TB2S
Timer B2 count start flag
Symbol
b2
b1
b0
CPSRF
Bit symbol
Nothing is assigned. When write, set to "0". When read, their
(b6-b0)
contents are indeterminate.
CPSR
Clock prescaler reset flag
page 110
f o
3
2
9
6
C
2 /
6
) T
Symbol
Address
TB0
0391
TB1
0393
TB2
0395
Function
Divide the count source by n + 1
where n = set value
Divide the count source by n + 1
where n = set value (2)
Measures a pulse period or width
Divide the count source by n + 1 where
n = set value and cause the timer stop
Address
After reset
0380
00
16
Bit name
0 : Stops counting
1 : Starts counting
Address
After reset
0381
0XXXXXXX
16
Bit name
Setting this bit to "1" initializes the
prescaler for the timekeeping clock.
(When read, the value of this bit is "0".)
After reset
, 0390
Indeterminate
16
16
, 0392
Indeterminate
16
16
, 0394
Indeterminate
16
16
Setting range
0000
to FFFF
16
16
0000
to FFFF
16
16
0000
to FFFF
16
16
16
Function
2
Function
12. Timer
RW
RW
RW
RO
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
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