Table of Contents
Advertisement
M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
Table 11.1 DMAC Specifications
Item
No. of channels
Transfer memory space
Maximum No. of bytes transferred
DMA request factors
Channel priority
Transfer unit
Transfer address direction
Transfer mode Single transfer
Repeat transfer When the DMAi transfer counter underflows, it is reloaded with the value
DMA interrupt request generation timing When the DMAi transfer counter underflowed
DMA startup
DMA shutdown Single transfer
Repeat transfer When the DMAE bit is set to "0" (disabled)
N OTES:
1. DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the I flag nor by the
interrupt control register.
2. The selectable causes of DMA requests differ with each channel.
3. Make sure that no DMAC-related registers (addresses 0020
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
6
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
2 (cycle steal method)
• From any address in the 1M bytes space to a fixed address
• From a fixed address to any address in the 1M bytes space
• From a fixed address to a fixed address
128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
(1, 2)
Falling edge of INT0 or INT1
Both edge of INT0 or INT1
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B2 interrupt requests
UART0 transfer, UART0 reception interrupt requests
UART1 transfer, UART1 reception interrupt requests
UART2 transfer, UART2 reception interrupt requests
A/D conversion interrupt requests
Software triggers
DMA0 > DMA1 (DMA0 takes precedence)
8 bits or 16 bits
forward or fixed (The source and destination addresses cannot both be
in the forward direction.)
Transfer is completed when the DMAi transfer counter (i = 0,1)
underflows after reaching the terminal count.
of the DMAi transfer counter reload register and a DMA transfer is con
tinued with it.
Data transfer is initiated each time a DMA request is generated when the
DMAE bit in the DMAiCON register is set to "1" (enabled).
• When the DMAE bit is set to "0" (disabled)
• After the DMAi transfer counter underflows
When a data transfer is started after setting the DMAE bit to "1" (en
abled), the forward address pointer is reloaded with the value of the
SARi or the DARi pointer whichever is specified to be in the forward
direction and the DMAi transfer counter is reloaded with the value of the
DMAi transfer counter reload register.
page 83
f o
3
2
9
6
C
2 /
6
) T
Specification
________
________
________
________
to 003F
16
) are accessed by the DMAC.
16
11. DMAC
Advertisement
Table of Contents
