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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
6
ROM Code Protect Control Address
b7
b6
b5
b4
b3
1
1
1
NOTES:
1. When the ROM code protect is active by the ROMCP1 bit setting, the flash memory is protected
against reading or rewriting in parallel I/O mode.
2. Set the bit 5 to bit 0 to 111111
0 are set to values other than 111111
ROMCP1 bit to a value other than 11
3. To make the ROM code protection inactive, erase a block including the ROMCP address in standard
serial I/O mode or CPU rewrite mode.
4. The ROMCP address is set to FF
5. When a value of the ROMCP address is 00
Figure 17.3.1.1. ROMCP Address
Figure 17.3.2.1. Address for ID Code Stored
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
6
b2
b1
b0
Symbol
1
1
1
ROMCP
Bit Symbol
Reserved Bit
(b5-b0)
ROM Code Protect Level
ROMCP1
1 Set Bit
when the ROMCP1 bit is set to a value other than 11
2
when a block, including the ROMCP address, is erased.
16
Address
0FFFDF
to 0FFFDC
16
16
0FFFE3
to 0FFFE0
16
16
0FFFE7
to 0FFFE4
16
16
0FFFEB
to 0FFFE8
16
16
0FFFEF
to 0FFFEC
16
16
0FFFF3
to 0FFFF0
16
16
0FFFF7
to 0FFFF4
16
16
0FFFFB
to 0FFFF8
16
16
0FFFFF
to 0FFFFC
16
16
page 236
f o
3
2
9
C
2 /
6
) T
(5)
Address
Factory Setting
0FFFFF
FF
16
Bit Name
Set to 1
b7 b6
00:
(1, 2, 3, 4)
01:
10:
11: Disables protect
, the ROM code protection may not become active by setting the
2
.
2
or FF
, the ROM code protect function is disabled.
16
16
ID1
Undefined instruction vector
ID2
Overflow vector
BRK instruction vector
ID3
Address match vector
ID4
Single step vector
ID5
Watchdog timer vector
ID6
DBC vector
ID7
NMI vector
Reset vector
ROMCP
4 bytes
17. Flash Memory Version
(4)
16
Function
}
Enables protect
. If the bit 5 to bit
2
RW
RW
RW
RW
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