Table of Contents
Advertisement
M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
UARTi transmit/receive mode register (i = 0, 1)
b7
b6
b5
b4
b3
b2
NOTES:
1. Set the corresponding port direction bit for each CLKi pin to "0" (input mode).
2. To receive data, set the corresponding port direction bit for each RxDi pin to "0" (input mode).
UART2 transmit/receive mode register
b7
b6
b5
b4
b3
b2
NOTES:
1. Set the corresponding port direction bit for each CLK2 pin to "0" (input mode).
2. To receive data, set the corresponding port direction bit for each RxD2 pin to "0" (input mode).
3. Set the corresponding port direction bit for SCL2 and SDA2 pins to "0" (input mode).
Figure 13.1.5. U0MR to U2MR registers
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
6
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
b1
b0
Symbol
U0MR, U1MR
Bit
Bit name
symbol
SMD0
Serial I/O mode select bit
(2)
SMD1
SMD2
Internal/external clock
CKDIR
select bit
STPS
Stop bit length select bit
PRY
Odd/even parity select bit
PRYE
Parity enable bit
Reserve bit
(b7)
b1
b0
Symbol
U2MR
Bit
Bit name
symbol
SMD0
Serial I/O mode select bit
(2)
SMD1
SMD2
CKDIR
Internal/external clock
select bit
STPS
Stop bit length select bit
PRY
Odd/even parity select bit
PRYE
Parity enable bit
TxD, RxD I/O polarity
IOPOL
reverse bit
page 137
f o
3
2
9
6
C
2 /
6
) T
Address
After reset
03A0
, 03A8
00
16
16
16
b2 b1 b0
0 0 0 : Serial I/O disabled
0 0 1 : Clock synchronous serial I/O mode
1 0 0 : UART mode transfer data 7 bits long
1 0 1 : UART mode transfer data 8 bits long
1 1 0 : UART mode transfer data 9 bits long
Do not set value other than the above
0 : Internal clock
1 : External clock (1)
0 : One stop bit
1 : Two stop bits
Effective when PRYE = 1
0 : Odd parity
1 : Even parity
0 : Parity disabled
1 : Parity enabled
Write to "0"
Address
After reset
0378
00
16
16
b2 b1 b0
0 0 0 : Serial I/O disabled
0 0 1 : Clock synchronous serial I/O mode
2
0 1 0 : I
C bus mode
1 0 0 : UART mode transfer data 7 bits long
1 0 1 : UART mode transfer data 8 bits long
1 1 0 : UART mode transfer data 9 bits long
Must not be set except above
0 : Internal clock
1 : External clock (1)
0 : One stop bit
1 : Two stop bits
Effective when PRYE = 1
0 : Odd parity
1 : Even parity
0 : Parity disabled
1 : Parity enabled
0 : No reverse
1 : Reverse
Function
Function
(3)
13. Serial I/O
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Advertisement
Table of Contents
