Table of Contents
Advertisement
M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
6
•Example 3: When AD
pin input
AD
TRG
AN
0
AN
1
AN
2
AN
3
"1"
ADST flag
"0"
"1"
ADERR0 flag
"0"
"1"
ADERR1 flag
"0"
"1"
ADTCSF flag
"0"
"1"
ADSTT0 flag
"0"
"1"
ADSTT1 flag
"0"
"1"
ADSTRT0 flag
"0"
"1"
ADSTRT1 flag
"0"
"1"
IR bit in the ADIC
"0"
register
ADST flag: Bit 6 in the ADCON0 register
ADERR0, ADERR1, ADTCSF, ADSTT0, ADSTT1, ADSTRT0 and ADSTRT1 flag: bits 0, 1, 3, 4, 5, 6 and 7 in the ADSTAT0 register
Figure 14.1.8.2 Each Flag Operation in ADSTAT0 Register Associated with the Operation Example
in Delayed Trigger Mode 1 (2)
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
6
input falling edge is generated more than two times after AN
TRG
Do not set to "1" by program
Set to "0" when interrupt request acknowledgement or a program
page 208
f o
3
2
9
C
2 /
6
) T
(invalid)
Set to "0" by program
pin conversion
0
A/D pin input
voltage sampling
A/D pin conversion
(valid after single sweep conversion)
14. A/D Converter
Advertisement
Table of Contents
