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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
6
Flash memory control register 0
b7 b6 b5 b4 b3 b2 b1 b0
0
0
NOTES:
1. When setting this bit to "1", set to "1" immdediately after setting it first to "0". Do not generate an interrupt
or a DMA transfer between setting the bit to "0" and setting it to "1". Set this bit while the P8
is "H" when selecting the NMI function. Set by program in a space other than the flash memory in EW0
mode. Set this bit to read alley mode and "0"
2. Set this bit to "1" immediately after setting it first to "0" while the FMR01 bit is set to "1". Do not generate
an interrupt or a DMA transfer between setting this bit to "0" and setting it to "1".
3. Set this bit in a pace other than the flash memory by program. When this bit is set to 1, access to flash
memory will be denied. To set this bit to 0 after setting it to 1, wait for 10
1. To read data from flash memory after setting this bit to 0, maintain tps wait time before accessing
flash memory.
4. This bit is set to "0" by executing the clear status command.
5. This bit is enabled when the FMR01 bit is set to "1" (CPU rewrite mode). This bit can be set to "1" when
the FMR01 bit is set to "0". However, the flash memory does not enter low-power consumption status
Flash memory control register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
NOTES:
1. Set this bit to "1" immediately after setting it first to "0". Do not generate an interrupt or a DMA transfer
between setting the bit to "0" and setting it to "1". Set this bit while the P8
NMI function is selected. If the FMR01 bit is set to "0", the FMR01 bit and FMR11 bit are both set to "0"
2. Set this bit to "1" immediately after setting it first to "0". Do not generate an interrupt or a DMA transfer
after setting to "0".
3. When rewriting more than 100 times, set this bit to "1" (with wait state). When the FMR17 bit is "1" (with
wait state), regardless of the content of the PM17 bit, 1 wait is inserted at the access to the block A and
B. Regardless of the content of the FMR17 bit, access to other block and the internal RAM is
determined be PM17 bit setting.
Figure 17.5.1. FMR0 and FMR1 register
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
6
Symbol
FMR0
Bit symbol
RY/BY status flag
FMR00
CPU rewrite mode select bit
FMR01
(1)
Block 0, 1 rewrite enable bit
FMR02
(2)
Flash memory stop bit
FMSTP
(3, 5)
Reserved bit
(b5-b4)
Program status flag
FMR06
FMR07
Erase status flag
Symbol
FMR1
Bit symbol
Reserved bit
(b0)
FMR11
EW1 mode select bit (1)
Reserved bit
(b3-b2)
Nothing is assigned. When write, set to "0".
(b4)
When read, its contect is indeterminate.
Reserved bit
(b5)
Block 0 to 3 rewrite enable
FMR16
bit (2)
Block A, B access wait bit
FMR17
(3)
page 241
f o
3
2
9
C
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6
) T
Address
After reset
01B7
00000001
16
2
Bit name
0: Busy (during writing or erasing)
1: Ready
0: Disables CPU rewrite mode
(Disables software command)
1: Enables CPU rewrite mode
(Enables software commands)
Set write protection for user ROM area
(see Table 17.5.2.1)
0: Starts flash memory operation
1: Stops flash memory operation
(Enters low-power consumption state
and flash memory reset)
Set to "0"
0: Terminated normally
(4)
1: Terminated in error
0: Terminated normally
1: Terminated in error
(4)
Address
After reset
01B5
000XXX0X
16
2
Bit name
When read, its content is indeterminate
0: EW0 mode
1: EW1 mode
When read, its content is indeterminate
Set to "0"
Set write protection for user ROM area
(see Table 17.5.2.1)
0: Disable
1: Enable
0: PM17 enabled
1: With wait state (1 wait)
17. Flash Memory Version
Function
RW
RO
RW
RW
RW
RW
RO
RO
/NMI/SD pin
5
µ
sec. or more after setting it to
Function
RW
RO
RW
RO
RW
RW
RW
/NMI/SD pin is "H" when the
5
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