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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
CM10=1(stop mode)
WAIT instruction
RESET
Software reset
NMI
Interrupt request level judgment output
CM00, CM01, CM02, CM04, CM05, CM06, CM07: CM0 register bits
CM10, CM11, CM16, CM17: CM1 register bits
PCLK0, PCLK1, PCLK5: PCLKR register bits
CM21, CM27
: CM2 register bits
Oscillation stop, re-oscillation detection circuit
Pulse generation
Charge,
circuit for clock
Main
discharge
edge detection
clock
circuit
and charge,
discharge control
Main clock
Figure 7.1. Clock Generation Circuit
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
6
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
Sub-clock
generating circuit
X
X
CIN
COUT
CM04
CM21
S
Q
X
X
IN
OUT
R
Main clock
generating circuit
CM05
S
Q
R
Reset
CM27=0
generating
circuit
Oscillation stop,
re-oscillation
CM27=1
detection interrupt
generating circuit
PLL frequency synthesizer
Programmable
counter
Phase
comparator
page 39
f o
3
2
9
6
C
2 /
6
) T
I/O ports
Sub-clock
On-chip
oscillator
clock
Oscillation
stop, re-
oscillation
detection
circuit
PLL
frequency
synthesizer
PLL
CM21=1
clock
Main
1
clock
0
CM21=0
CM11
CM02
e
1/2
1/2
a
1/2
CM06=0
CM17-CM16=01
CM06=0
CM17-CM16=00
2
On-chip Oscillator
ROCR1-ROCR0=00
f
1(ROC)
Oscillation stop
detection reset
f
2(ROC)
ROCR1-ROCR0=01
Oscillation stop,
re-oscillation
detection signal
f
3(ROC)
ROCR1-ROCR0=11
CM21 switch signal
Charge
pump
7. Clock Generation Circuit
PCLK5=0,CM01-CM00=00
2
PCLK5=0,CM01-CM00=01
2
PCLK5=1,
PCLK5=0,
CM01-CM00=00
2
CM01-CM00=10
2
f
C32
1/32
f
1
PCLK0=1
f
2
PCLK0=0
f
C
f
8
f
32
f
AD
f
1SIO
PCLK1=1
f
2SIO
PCLK1=0
f
8SIO
f
32SIO
c
e
b
a
CM07
0
=
d
f
C
CM07
1
=
b
1/2
1/2
1/4
1/8
1/16
CM06=1
CM06=0
CM17-CM16=10
2
2
Details of divider
2
1/2
1/2
2
2
ROCR3-ROCR2=10
ROCR3-ROCR2=01
2
1/2
PLL clock
Voltage
control
oscillator
(VCO)
Internal low-
pass filter
CLK
OUT
PCLK5=0,
CM01-CM00=11
2
D4INT clock
CPU clock
BCLK
c
1/2
1/32
CM06=0
CM17-CM16=11
2
d
1/2
ROCR3-ROCR2=11
2
2
On-chip
oscillator
clock
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