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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
6
• Main clock
f
1
• PLL clock
• On-chip
oscillator clock
f
f
f
1 or
2
8
TB0
IN
TB1
IN
TB2
IN
Figure 12.2. Timer B Configuration
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
6
f
2
PCLK0 bit = "0"
1/2
PCLK0 bit = "1"
1/8
1/4
f
f
32
C32
Timer B2 overflow or underflow ( to Timer A count source)
Noise
filter
Noise
filter
Noise
filter
page 93
f o
3
2
9
C
2 /
6
) T
f
f
1 or
2
X
CIN
f
8
Set the CPSR bit in the
CPSRF register to "1"
f
32
(= prescaler reset)
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
• Event counter mode
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
• Event counter mode
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
• Event counter mode
Clock prescaler
f
C32
1/32
Reset
Timer B0 interrupt
Timer B0
Timer B1 interrupt
Timer B1
Timer B2 interrupt
Timer B2
12. Timer
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