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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
6
Address match interrupt enable register
b7
b6
b5
b4
b3
Address match interrupt register i (i = 0 to 1)
(b19)
(b23)
b7
b3
Figure 9.9.1. AIER Register, RMAD0 and RMAD1 Registers
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
b2
b1
b0
Symbol
AIER
Bit symbol
AIER0
AIER1
(b7-b2)
(b16)
(b15)
(b8)
b0 b7
b0
b7
Address setting register for address match interrupt
Nothing is assigned.
When write, set to "0".
When read, their contents are indeterminate.
page 79
f o
3
2
9
6
C
2 /
6
) T
Address
0009
XXXXXX00
16
Bit name
Address match interrupt 0
enable bit
Address match interrupt 1
enable bit
Nothing is assigned.
When write, set to "0".
When read, their contents are indeterminate.
Symbol
b0
RMAD0
RMAD1
Function
After reset
2
Function
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Address
0012
to 0010
16
16
0016
to 0014
16
16
Setting range
00000
to FFFFF
16
9. Interrupt
RW
RW
RW
After reset
X00000
16
X00000
16
RW
RW
16
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