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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
6
V o l t a g e d e t e c t i o n r e g i s t e r 1
b7
b6
b 5
0 0 0 0
NOTES:
1. The VC13 bit is useful when the VC27 bit in the VCR2 register is set to "1" (voltage down detection circuit
enable). The VC13 bit is always "1" (VCC ≥ Vdet4) when the VC27 bit in the VCR2 register is set to "0"
(voltage down detection circuit disable).
2. This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
V o l t a g e d e t e c t i o n r e g i s t e r 2 (1)
b7
b6
b 5
0
0 0 0 0 0
NOTES:
1. Write to this register after setting the PRC3 bit in the PRCR register to "1" (write enable).
2. When not in stop mode, to use hardware reset 2, set the VC26 bit to "1" (reset level detection circuit enable).
3. VC26 bit is disabled in stop mode. (The microcomputer is not reset even if the voltage input to Vcc pin
becomes lower than Vdet3.)
4. When the VC13 bit in the VCR1 register and D42 bit in the D4INT register are used or the D40 bit is set to
"1" (voltage down detection interrupt enable), set the VC27 bit to "1" (voltage down detection circuit enable).
5. This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
6. The detection circuit does not start operation until td(E-A) elapses after the VC26 bit, or VC27 bit are set to
"1".
V o l t a g e d o w n d e t e c t i o n i n t e r r u p t r e g i s t e r (1)
b 7
b 6
b 5
NOTES:
1. Write to this register after setting the PRC3 bit in the PRCR register to "1" (write enable).
2. Useful when the VC27 bit in the VCR2 register is set to "1" (voltage down detection circuit enabled). If the
VC27 bit is set to "0" (voltage down detection circuit disable), the D42 bit is set to "0" (Not detect).
3. This bit is set to "0" by writing a "0" in a program. (Writing a "1" has no effect.)
4. If the voltage down detection interrupt needs to be used to get out of stop mode again after once used for
that purpose, reset the D41 bit by writing a "0" and then a "1".
5. The D40 bit is effective when the VC27 bit in the VCR2 register is set to "1". To set the D40 bit to "1", follow
the procedure described below.
(1) Set the VC27 bit to "1".
(2) Wait for td(E-A) until the detection circuit is actuated.
(3) Wait for the sampling time (refer to "Table 5.5.1.2 Sampling Clock Periods").
(4) Set the D40 bit to "1".
Figure 5.5.2. VCR1 Register, VCR2 Register, and D4INT Register
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
b 4
b 3
b 2
b 1
b 0
S y m b o l
0 0 0
V C R 1
B i t s y m b o l
R e s e r v e d b i t
( b 2 - b 0 )
V o l t a g e d o w n m o n i t o r f l a g
VC13
R e s e r v e d b i t
( b 7 - b 4 )
b 4
b 3
b 2
b 1
b 0
S y m b o l
V C R 2
B i t s y m b o l
Reserved bit
( b 5 - b 0 )
Reset level monitor bit
V C 2 6
(2, 3, 6)
VC27
Voltage down monitor
bit (4, 6)
b 4
b 3
b 2
b 1
b 0
S y m b o l
D 4 I N T
B i t s y m b o l
D 4 0
interrupt enable bit (5)
STOP mode deactivation
D 4 1
control bit
(4)
Voltage change detection flag
D 4 2
(2)
WDT overflow detect flag
D43
Sampling clock select bit
DF0
D F 1
Nothing is assigned. When write, set to "0". When read, its
(b7-b6)
content is "0".
page 30
f o
3
2
9
6
C
2 /
6
) T
A d d r e s s
A f t e r r e s e t ( 2)
0 0 1 9
0 0 0 0 1 0 0 0
1 6
2
Bit name
M u s t se t t o " 0 "
0:V
< Vdet4
CC
≥ Vdet4
(1)
1:V
CC
M u s t s e t t o " 0 "
A d d r e s s
A f t e r r e s e t (5)
0 0 1 A
0 0
1 6
1 6
B i t n a m e
Must set to "0"
0 : D i s a b l e r e s e t l e v e l d e t e c t i o n
c i r c u i t
1 : E n a b l e r e s e t l e v e l d e t e c t i o n
c i r c u i t
0: Disable voltage down
detection circuit
1: Enable voltage down
detection circuit
A d d r e s s
A f t e r r e s e t
0 0 1 F
0 0
1 6
1 6
Bit name
Disable
0 :
Enable
1 :
0 : D i s a b l e ( d o n o t u s e t h e v o l t a g e
d o w n d e t e c t i o n
i n t e r r u p t t o g e t o u t o f s t o p m o d e )
1 : E n a b l e ( u s e t h e v o l t a g e d o w n
d e t e c t i o n i n t e r r u p t t o g e t
o u t o f s t o p m o d e )
0: Not detected
1: Vdet4 passing detection
0 : N o t d e t e c t e d
1 : D e t e c t e d
b 5b4
0 0 : C P U c l o c k d i v i d e d b y 8
0 1 : C P U c l o c k d i v i d e d b y 1 6
1 0 : C P U c l o c k d i v i d e d b y 3 2
1 1 : C P U c l o c k d i v i d e d b y 6 4
F unction
RW
RW
RO
RW
RW
F u n c t i o n
RW
RW
RW
RW
Function
RW
RW
RW
(3)
RW
(3)
R W
R W
5. Reset
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