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(1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address
CPU clock
Address
bus
RD signal
WR signal
Data
bus
(2) When the transfer unit is 16 bits and the source address of transfer is an odd address
CPU clock
Address
bus
RD signal
WR signal
Data
bus
(3) When the source read cycle under condition (1) has one wait state inserted
CPU clock
Address
bus
RD signal
WR signal
Data
bus
(4) When the source read cycle under condition (2) has one wait state inserted
CPU clock
Address
CPU use
bus
RD signal
WR signal
Data
bus
NOTE:
1. The same timing changes occur with the respective conditions at the destination as at the source.
Figure 11.1.1 Transfer Cycles for Source Read
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2
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7
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2
0
2
0 -
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CPU use
Source
CPU use
Source
CPU use
Source
Source + 1
CPU use
Source
CPU use
Source
CPU use
Source
Source
CPU use
Source
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Dummy
Destination
cycle
Dummy
Destination
cycle
Dummy
Destination
cycle
Source + 1
Destination
Dummy
Destination
cycle
Destination
Source + 1
Source + 1
CPU use
CPU use
CPU use
Dummy
CPU use
cycle
CPU use
Dummy
CPU use
cycle
Dummy
Destination
CPU use
cycle
Dummy
Destination
cycle
11. DMAC
CPU use
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