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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
DMA1 request cause select register
b7
b6
b5
b4
b3
NOTE:
1. The causes of DMA1 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the
manner described below.
DSEL3 to DSEL0
0 0 0 0
2
0 0 0 1
2
0 0 1 0
2
0 0 1 1
2
0 1 0 0
2
0 1 0 1
2
0 1 1 0
2
0 1 1 1
2
1 0 0 0
2
1 0 0 1
2
1 0 1 0
2
1 0 1 1
2
1 1 0 0
2
1 1 0 1
2
1 1 1 0
2
1 1 1 1
2
DMAi control register
b7
b6
b5
b4
b3
NOTES:
1.The DMAS bit can be set to "0" by writing "0" in a program (This bit remains unchanged even if "1" is written).
2. At least one of the DAD and DSD bits must be "0" (address direction fixed).
Figure 11.3 DM1SL Register, DM0CON Register, and DM1CON Register
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
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6
, A
M
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M
1
Symbol
b2
b1
b0
DM1SL
Bit symbol
DSEL0
DMA request cause
select bit
DSEL1
DSEL2
DSEL3
Nothing is assigned. When write, set to "0".
(b5-b4)
When read, its content is "0".
DMA request cause
DMS
expansion select bit
Software DMA
request bit
DSR
DMS=0(basic cause of request)
Falling edge of INT1 pin
Software trigger
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
UART0 transmit
UART0 receive
UART2 transmit
UART2 receive/ACK2
A/D conversion
UART1 receive
(i=0,1)
Symbol
b2
b1
b0
DM0CON
DM1CON
Bit symbol
Transfer unit bit select bit
DMBIT
Repeat transfer mode
DMASL
select bit
DMA request bit
DMAS
DMA enable bit
DMAE
Source address direction
DSD
select bit (2)
Destination address
DAD
direction select bit (2)
Nothing is assigned. When write, set to "0". When
(b7-b6)
read, its content is "0".
page 85
f o
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) T
Address
After reset
03BA
16
Bit name
Refer to note
0: Basic cause of request
1: Extended cause of request
A DMA request is generated by
setting this bit to "1" when the DMS
bit is "0" (basic cause) and the
DSEL3 to DSEL0 bits are "0001
(software trigger).
The value of this bit when read is "0" .
DMS=1(extended cause of request)
–
–
–
–
–
–
–
Two edges of INT1
–
–
–
–
–
–
–
–
Address
After reset
002C
00000X00
16
003C
00000X00
16
Bit name
0 : 16 bits
1 : 8 bits
0 : Single transfer
1 : Repeat transfer
0 : DMA not requested
1 : DMA requested
0 : Disabled
1 : Enabled
0 : Fixed
1 : Forward
0 : Fixed
1 : Forward
00
16
Function
RW
RW
RW
RW
RW
RW
RW
"
2
2
2
Function
RW
RW
RW
RW
(1)
RW
RW
RW
11. DMAC
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