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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
6
A/D conversion status register 0 (1)
b7
b6
b5
b4
b3
b2
NOTE:
1. ADSTAT0 register is valid only when the DTE bit in the ADTRGCON register is set to "1".
A/D Register i (i=0 to 7)
(b15)
b7
Figure 14.4 ADSTAT0 Register and AD0 to AD7 Registers
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
6
b1
b0
Symbol
ADSTAT0
Bit symbol
AN1 Trigger Status Flag
ADERR0
ADERR1
Conversion Termination
Flag
Nothing is assigned. When write, set to "0".
(b2)
When read, its content is "0".
Delayed Trigger Sweep
ADTCSF
Status Flag
AN0 Conversion Status
ADSTT0
Flag
AN1 Conversion Status
ADSTT1
Flag
AN0 Conversion
ADSTRT0
Completion Status Flag
AN1 Conversion
ADSTRT1
Completion Status Flag
Symbol
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
(b8)
b0
b7
When the BITS bit in the ADCON1
register is "1" (10-bit mode)
Eight low-order bits of
A/D conversion result
Two high-order bits of
A/D conversion result
Nothing is assigned. When write, set to "0".
When read, its content is "0".
page 184
f o
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2
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6
) T
Address
After reset
03D3
00
16
Bit name
0 : AN1 trigger did not occur during
AN0 conversion
1 : AN1 trigger occured during AN0
conversion
0 : Conversion not terminated
1 : Conversion terminated by
Timer B0 underflow
0 : Sweep not in progress
1 : Sweep in progress
0 : AN0 conversion not in progress
1 : AN0 conversion in progress
0 : AN1 conversion not in progress
1 : AN1 conversion in progress
0 : AN0 conversion not completed
1 : AN0 conversion completed
0 : AN1 conversion not completed
1 : AN1 conversion completed
Address
After reset
03C1
to 03C0
Indeterminate
16
16
03C3
to 03C2
Indeterminate
16
16
03C5
to 03C4
Indeterminate
16
16
03C7
to 03C6
Indeterminate
16
16
03C9
to 03C8
Indeterminate
16
16
03CB
to 03CA
Indeterminate
16
16
03CD
to 03CC
Indeterminate
16
16
03CF
to 03CE
Indeterminate
16
16
b0
Function
When the BITS bit in the ADCON1
register is "0" (8-bit mode)
A/D conversion result
When read, its content is
indeterminate
16
Function
14. A/D Converter
RW
RW
RW
RO
RO
RO
RW
RW
RW
RO
RO
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