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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
6
19.10 Programmable I/O Ports
1. If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to "1"
(three-phase output forcible cutoff by input on SD pin enabled), the P7
a high-impedance state.
2. The input threshold voltage of pins differs between programmable input/output ports and peripheral
functions.
Therefore, if any pin is shared by a programmable input/output port and a peripheral function and the
input level at this pin is outside the range of recommended operating conditions V
"high" nor "low"), the input level may be determined differently depending on which side—the program-
mable input/output port or the peripheral function—is currently selected.
3. When the INV03 bit in the INVC0 register is "1"(three-phase motor control timer output enabled), an "L"
input on the P8
•When the IVPCR1 bit in the TB2SC register is set to "1" (three-phase output forcible cutoff by input
_____
on the SD pin enabled), the U/ U/ V/ V/ W/ W pins go to a high-impedance state.
•When the IVPCR1 bit is set to "0" (three-phase output forcible cutoff by input on SD pin
disabled), the U/ U/ V/ V/ W/ W pins go to a normal port.
Therefore, the P8
_____
When the SD function isn't used, set PD8
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
6
_____
_______ _____
/NMI/SD pin, has the following effect:
5
__
__
__
___
pin can not be used as programmable I/O port when the INV03 bit is set to "1".
5
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f o
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2
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) T
_____
__
___
to "0" (Input) and pull the P8
5
19. Usage Notes
to P7
, P8
and P8
pins go to
2
5
0
1
and V
IH
IL
_____
_______ _____
/NMI/SD pin to "H" externally.
5
(neither
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