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13.1.2.4. Serial Data Logic Switching Function (UART2)
The data written to the U2TB register has its logic reversed before being transmitted. Similarly, the
received data has its logic reversed when read from the U2RB register. Figure 13.1.2.4.1 shows serial
data logic.
(1) When the U2LCH bit in the U2C1 register is set to "0" (no reverse)
"H"
Transfer clock
TxD
"H"
2
(no reverse)
"L"
(2) When the U2LCH bit in the U2C1 register is set "1" (reverse)
"H"
Transfer clock
"L"
"H"
TxD
2
(reverse)
"L"
NOTE:
1. This applies to the case where the CKPOL bit in the U2C0 register is set to "0"
(transmit data output at the falling edge of the transfer clock), the UFORM bit in the
U2C0 register is set to "0" (LSB first), the STPS bit in the U2MR register is set to "0"
(1 stop bit) and the PRYE bit in the U2MR register is set to "1" (parity enabled).
Figure 13.1.2.4.1. Serial Data Logic Switching
13.1.2.5. TxD and RxD I/O Polarity Inverse Function (UART2)
This function inverses the polarities of the T
input/output data (including the start, stop and parity bits) are inversed. Figure 13.1.2.5.1 shows the
T
D pin output and R
X
(1) When the IOPOL bit in the U2MR register is set to "0" (no reverse)
Transfer clock
TxD
2
(no reverse)
RxD
2
(no reverse)
(2) When the IOPOL bit in the U2MR register is set to "1" (reverse)
Transfer clock
TxD
2
(reverse)
RxD
2
(reverse)
NOTE:
1. This applies to the case where the UFORM bit in the U2C0 register is set to
"0"(LSB first), the STPS bit in the U2MR register is set to "0" (1 stop bit) and the
PRYE bit in the U2MR register is set to "1"(parity enabled).
Figure 13.1.2.5.1. T
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2
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0
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2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
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6
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, B
M
1
"L"
ST
D0
D1
D2
ST
D0
D1
D2
D pin input polarity inverse.
X
"H"
"L"
"H"
ST
D0
D1
"L"
"H"
ST
D0
D1
"L"
"H"
"L"
"H"
ST
D0
D1
"L"
"H"
ST
D0
D1
"L"
D and R
D I/O Polarity Inverse
X
X
page 156
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) T
D3
D4
D5
D6
D7
D3
D4
D5
D6
D7
D2 pin output and R
X
D2
D3
D4
D5
D6
D7
D2
D3
D4
D5
D6
D7
D2
D3
D4
D5
D6
D7
D2
D3
D4
D5
D6
D7
P
SP
P
SP
ST: Start bit
P: Parity bit
SP: Stop bit
D2 pin input. The logic levels of all
X
P
SP
P
SP
P
SP
P
SP
ST: Start bit
P: Parity bit
SP: Stop bit
13. Serial I/O
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