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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
6
1.5 Pin Assignments
Figures 1.6 and 1.7 show the Pin Assignments (top view).
P10
/AN
/KI
7
7
3
P10
/AN
/KI
6
6
2
P10
/AN
/KI
5
5
1
P10
/AN
/KI
4
4
0
P10
/AN
3
3
P10
/AN
2
2
P10
/AN
1
1
AV
ss
P10
/AN
0
0
V
REF
AV
cc
P9
/AN
3
24
Figure 1.6 Pin Assignment for 48-Pin Package (Top View)
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
6
37
38
39
40
41
42
43
44
45
46
47
48
page 11
f o
3
2
9
C
2 /
6
) T
24
P7
/RxD
1
P7
/CLK
23
2
22
P7
/CTS
3
21
P7
/TA2
4
20
P7
/TA2
5
19
P7
/TA3
6
18
P7
/TA3
7
17
P8
/TA4
0
16
P8
/TA4
1
15
P8
/INT
2
P8
/INT
14
3
P8
/INT
13
4
NOTE:
1. Set PACR2 to PACR0 bit in the PACR register
to "100
resetting to each pin. When the PACR register
isn't set up, the input and output function of
some of the pins are disabled.
Package: PLQP0048KB-A (48P6Q)
/TA0
/SCL
/CLK
2
IN
2
1
/TA1
/V/RxD
2
OUT
1
/RTS
/TA1
/V/TxD
2
2
IN
1
/W
OUT
/W
IN
OUT
IN
/U
OUT
/U
IN
0
1
/ZP
2
" before you input and output it after
2
1. Overview
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