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Table 13.1.3.2.1. STSPSEL Bit Functions
Function
Output of SCL2 and SDA2 pins
Start/stop condition interrupt
request generation timing
(1) In slave mode,
CKDIR is set to "1" (external clock)
STPSEL bit
SCL2
SDA2
(2) In master mode,
CKDIR is set to "0" (internal clock), CKPH is set to "1"(clock delayed)
STPSEL bit
SCL2
SDA2
Set STAREQ to "1" (start)
Figure 13.1.3.2.1. STSPSEL Bit Functions
13.1.3.3 Arbitration
Unmatching of the transmit data and SDA
edge of SCL
2
U2RB register is updated. If the ABC bit is set to "0" (updated bitwise), the ABT bit is set to "1" at the
same time unmatching is detected during check, and is cleared to "0" when not detected. In cases
when the ABC bit is set to "1", if unmatching is detected even once during check, the ABT bit is set to
"1" (unmatching detected) at the falling edge of the clock pulse of 9th bit. If the ABT bit needs to be
updated bytewise, clear the ABT bit to "0" (undetected) after detecting acknowledge in the first byte,
before transferring the next byte.
Setting the ALS bit in the U2SMR2 register to "1" (SDA output stop enabled) causes arbitration-lost to
occur, in which case the SDA
is set to "1" (unmatching detected).
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STSPSEL = 0
Output transfer clock and data/
Program with a port determines
how the start condition or stop
condition is output
Start/stop condition are de-
tected
0
1st
2nd
Start condition detection
interrupt
Set to "1" by
Set to "0" by
a program
a program
1st
Start condition detection
interrupt
. Use the ABC bit in the U2SMR register to select the timing at which the ABT bit in the
pin is placed in the high-impedance state at the same time the ABT bit
2
page 165
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) T
3rd
4th
5th
6th
7th
8th
9th bit
Stop condition detection
interrupt
2nd
3rd
5th
6th
7th
4th
Set STPREQ
to "1" (start)
pin input data is checked synchronously with the rising
2
STSPSEL = 1
The STAREQ, RSTAREQ and
STPREQ bit determine how the
start condition or stop condition is
output
Start/stop condition generation are
completed
Set to "1" by
Set to "0" by
a program
a program
8th
9th bit
Stop condition detection
interrupt
13. Serial I/O
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