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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
Timer Bi mode register (i= 0 to 1)
b7
b6
b5
b4
b3
NOTE:
1. When this bit is used in delayed trigger mode 0, set the same count source to the timer B0 and timer B1.
Figure 12.2.4.1 TBiMR Register in A/D Trigger Mode
Timer B2 special mode register
b7
b6
b5
b4
b3
0
0
NOTES:
1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enabled).
2. If the INV11 bit is "0" (three-phase mode 0) or the INV06 bit is "1" (triangular wave modulation mode), set this bit to
"0" (timer B2 underflow).
3. When setting the IVPCR1 bit to "1" (three-phase output forcible cutoff by SD pin input enabled), Set the PD8_5 bit to
"0" (= input mode).
4. Related pins are U(P8
pin and set the IVPCR1 bit to 0 after forcible cutoff, pins U, U, V, V, W, and W are exit from the high-impedance state.
If a low-level ("L") signal is applied to the SD pin, three-phase motor control timer output will be disabled (INV03=0).
At this time, when the IVPCR1 bit is 0, pins U, U, V, V, W, and W become programmable I/O ports. When the IVPCR1
bit is set to 1, pins U, U, V, V, W, and W are placed in a high-impedance state regardless of which function of those
pins is used.
5. When this bit is used in delayed trigger mode 0, set the TB0EN and TB1EN bits to "1"(A/D trigger mode).
6. When setting the TB2SEL bit to "1" (underflow of TB2 interrupt generation frequency setting counter[ICTB2]), Set the
INV02 bit to "1" (three-phase motor control timer function).
7. Refer to 16.6 Digital Debounce function for SD input.
Figure 12.2.4.2 TB2SC Register
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
6
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
b2
b1
b0
Symbol
TB0MR to TB1MR
0
0
Bit symbol
TMOD0
Operation Mode Select Bit
TMOD1
MR0
Invalid in A/D trigger mode
Either "0" or "1" is enabled
MR1
TB0MR register
MR2
Set to "0" in A/D trigger mode
TB1MR register
Nothing is assigned. When write, set to "0". When read, its
content is indeterminate
MR3
When write in A/D trigger mode, set to "0". When read in A/D
trigger mode, its content is indeterminate.
Count Source Select Bit
TCK0
TCK1
(1)
b2
b1
b0
Symbol
Address
TB2SC
039E
Bit symbol
Bit name
PWCOM
Timer B2 Reload Timing
Switch Bit
Three-Phase Output Port
IVPCR1
SD Control Bit 1
Timer B0 Operation Mode
TB0EN
Select Bit
Timer B1 Operation Mode
TB1EN
Select Bit
TB2SEL
Trigger Select Bit
Reserved bits
(b6-b5)
Nothing is assigned. When write, set to "0".
(b7)
When read, its content is "0".
), U(P8
), V(P7
), V(P7
0
1
2
page 116
f o
3
2
9
6
C
2 /
6
) T
Address
After reset
039B
to 039C
00XX0000
16
16
Bit name
b1 b0
0 0 : Timer mode or A/D trigger mode
b7 b6
0 0 : f
or f
1
(1)
0 1 : f
8
1 0 : f
32
1 1 : f
C32
After reset
X0000000
16
2
Function
0 : Timer B2 underflow
(2)
1 : Timer A output at odd-numbered
0 : Three-phase output forcible cutoff
by SD pin input (high impedance)
disabled
(3, 4, 7)
1 : Three-phase output forcible cutoff
by SD pin input (high impedance)
enabled
0 : Other than A/D trigger mode
1 : A/D trigger mode
0 : Other than A/D trigger mode
1 : A/D trigger mode
(6)
0 : TB2 interrupt
1 : Underflow of TB2 interrupt
generation frequency setting counter [ICTB2]
Must set to "0"
), W(P7
), W(P7
). When a high-level ("H") signal is applied to the SD
3
4
5
2
Function
RW
RW
RW
RW
RW
RW
RO
RW
2
RW
RW
RW
RW
RW
(5)
RW
(5)
RW
RW
12. Timer
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