Table of Contents
Advertisement
M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
6
P6
, P6
3
7
P8
5
P9
, P9
,
1
2
P10
to P10
4
7
NOTE:
1.
Make sure the input voltage on each port will not exceed Vcc.
Figure 16.3. I/O Ports (3)
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
6
Direction register
Port latch
Data bus
Switching between CMOS and Nch
Pull-up selection
NMI Enable
Direction register
Data bus
Port latch
NMI Interrupt Input
Pull-up selection
Direction register
Data bus
Port latch
Input to respective peripheral functions
symbolizes a parasitic diode.
page 220
f o
3
2
9
C
2 /
6
) T
Pull-up selection
"1"
Output
Digital Debounce
NMI Enable
SD
Analog input
16. Programmable I/O Ports
(1)
(1)
(1)
Advertisement
Table of Contents
