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13.1.1.1 Counter Measure for Communication Error Occurs
If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode,
follow the procedures below.
•Resetting the UiRB register (i=0 to 2)
(1) Set the RE bit in the UiC1 register to "0" (reception disabled)
(2) Set the SMD2 to SMD0 bits in the UiMR register to "000
(3) Set the SMD2 to SMD0 bits in the UiMR register to "001
(4) Set the RE bit in the UiC1 register to "1" (reception enabled)
•Resetting the UiTB register (i=0 to 2)
(1) Set the SMD2 to SMD0 bits in the UiMR register to "000
(2) Set the SMD2 to SMD0 bits in the UiMR register to "001
(3) "1" is written to RE bit in the UiC1 register (reception enabled), regardless to the TE bit in the UiC1
register.
13.1.1.2 CLK Polarity Select Function
Use the CKPOL bit in the UiC0 register (i = 0 to 2) to select the transfer clock polarity. Figure 13.1.1.2.1
shows the polarity of the transfer clock.
(1) When the CKPOL bit in the UiC0 register is set to "0" (transmit data output at the falling
edge and the receive data taken in at the rising edge of the transfer clock)
CLK
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(2) When the CKPOL bit in the UiC0 register is set to "1" (transmit data output at the rising
edge and the receive data taken in at the falling edge of the transfer clock)
CLK
i
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R
D
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i
NOTES:
1. This applies to the case where the UFORM bit in the UiC0 register is set to "0" (LSB first) and the
UiLCH bit in the UiC1 register is set to "0" (no reverse).
2. When not transferring, the CLKi pin outputs a high signal.
3. When not transferring, the CLKi pin outputs a low signal.
i = 0 to 2
Figure 13.1.1.2.1. Polarity of transfer clock
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" (Serial I/O disabled)
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" (Clock synchronous serial I/O mode)
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" (Serial I/O disabled)
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" (Clock synchronous serial I/O mode)
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(3)
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13. Serial I/O
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