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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
(1) Transmit Timing
Transfer Clock
TE bit in U2C1
register
TI bit in U2C1
register
TxD
2
Parity Error Signal
returned from
Receiving End
(1)
RxD
pin Level
2
TXEPT bit in U2
C0 register
IR bit in S2TIC
register
The above timing diagram applies to the case where data is
transferred in the direct format.
• U2MR register STPS bit = 0 (1 stop bit)
• U2MR register PRY bit = 1 (even)
• U2C0 register UFORM bit = 0 (LSB first)
• U2C1 register U2LCH bit = 0 (no reverse)
• U2C1 register U2IRSCH bit = 1 (transmit is completed)
(2) Receive Timing
Transfer Clock
RE bit in U2C1
register
Transmit Waveform
from the
Transmitting End
TxD2
(2)
RxD
pin Level
2
RI bit in U2C1
register
IR bit in S2RIC
register
The above timing diagram applies to the case where data is
transferred in the direct format.
• U2MR register STPS bit = 0 (1 stop bit)
• U2MR register PRY bit = 1 (even)
• U2C0 register UFORM bit = 0 (LSB first)
• U2C1 register U2LCH bit = 0 (no reverse)
• U2C1 register U2IRSCH bit = 1 (transmit is completed)
NOTES:
1. Because TxD
signal sent back from receiver.
2. Because TxD
and the parity error signal received.
Figure 13.1.6.1. Transmit and Receive Timing in SIM Mode
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
6
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
Tc
"1"
"0"
"1"
"0"
Start
bit
ST
D
D
D
D
D
0
1
2
3
4
ST
D
D
D
D
D
0
2
3
1
4
"1"
"0"
"1"
"0"
TC
"1
"
"0
"
Start
bit
ST
D
D
D
D
D
0
1
2
3
4
ST
D
D
D
D
D
0
1
2
3
4
"1"
"0
"
"1"
"0"
and RxD
are connected, this is composite waveform consisting of the TxD
2
2
and RxD
are connected, this is composite waveform consisting of the transmitter's transmit waveform
2
2
page 177
f o
3
2
9
6
C
2 /
6
) T
Data is written to
the UARTi register
Data is transferred from the U2TB
register to the UART2 transmit
Parity
Stop
register
bit
bit
D
D
D
P
SP
ST
D
5
6
7
An "L" signal is applied from the SIM
card due to a parity error
D
ST
D
D
D
P
SP
7
5
6
An interrupt routine
detects "H" or "L"
Set to "0" by an interrupt request acknowledgement or by program
Tc = 16 (n + 1) / fi or 16 (n + 1) / f
fi : frequency of U2BRG count source (f
f
: frequency of U2BRG count source (external clock)
EXT
n : value set to U2BRG
Parity
Stop
bit
bit
D
D
D
P
SP
ST
D
5
6
7
D
D
D
P
SP
ST
D
5
6
7
Set to "0" by an interrupt request acknowledgement or by program
Tc = 16 (n + 1) / fi or 16 (n + 1) / f
fi : frequency of U2BRG count source (f
f
: frequency of U2BRG count source (external clock)
EXT
n : value set to U2BRG
D
D
D
D
D
D
D
P
SP
0
1
2
3
4
5
6
7
D
D
D
D
D
D
D
P
0
2
3
7
1
4
5
6
An interrupt routine detects
"H" or "L"
EXT
, f
, f
1SIO
2SIO
8SIO
SP
D
D
D
D
D
D
D
P
0
1
2
3
4
5
6
7
TxD
outputs "L" due
2
to a parity error
D
D
D
D
D
D
D
P
0
1
2
3
4
5
6
7
Read the U2RB register
EXT
, f
, f
1SIO
2SIO
8SIO
output and the parity error
2
13. Serial I/O
SP
, f
)
32SIO
SP
, f
)
32SIO
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