Table of Contents
Advertisement
M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
UART2 Special Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0
NOTES:
1: The BBS bit is set to "0" by writing "0" by program. (Writing "1" has no effect).
2: When a transfer begins, the SSS bit is set to "0" (Not synchronized to R
UART2 Special Mode Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Figure 13.1.8. U2SMR register and U2SMR2 register
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
6
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
Symbol
U2SMR
Bit
Bit Name
Symbol
2
IICM
I
C bus mode select bit
ABC
Arbitration lost detecting
flag control bit
BBS
Bus busy flag
Reserved bit
(b3)
Bus collision detect
ABSCS
sampling clock select bit
Auto clear function
ACSE
select bit of transmit
enable bit
Transmit start condition
SSS
select bit
Nothing is assigned. When write, set "0".
(b7)
When read, its content is indeterminate.
Symbol
U2SMR2
Bit
Bit Name
Symbol
2
I C bus mode select bit 2
IICM2
CSC
Clock-synchronous bit
SCL
wait output bit
SWC
2
ALS
SDA
output stop bit
2
UART initialization bit
STAC
SWC2
SCL
wait output bit 2
2
SDA
output disable bit
SDHI
2
Nothing is assigned. When write, set "0".
(b7)
When read, its content is indeterminate.
page 140
f o
3
2
9
6
C
2 /
6
) T
Address
After Reset
0377
X0000000
16
2
0 : Other than I
C bus mode
2
1 : I
C bus mode
0 : Update per bit
1 : Update per byte
0 : STOP condition detected
1 : START condition detected (busy)
Set to "0"
0 : Rising edge of transfer clock
1 : Underflow signal of timer A0
0 : No auto clear function
1 : Auto clear at occurrence of bus collision
0 : Not synchronized to R
1 : Synchronized to R
Di).
X
Address
After Reset
0376
X0000000
16
Refer to Table 13.12
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
0: Transfer clock
1: "L" output
0: Enabled
1: Disabled (high impedance)
2
Function
Di
X
(2)
Di
X
2
Function
13. Serial I/O
RW
RW
RW
RW
(1)
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Advertisement
Table of Contents
