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The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP
at the time of acceptance of an interrupt request, is even or odd. If the stack pointer
register and the PC are saved, 16 bits at a time. If odd, they are saved in two steps, 8 bits at a time.
Figure 9.4.3.2 shows the operation of the saving registers.
NOTE:
1. When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated
by the U flag. Otherwise, it is the ISP.
(1) SP contains even number
[SP] – 5 (Odd)
[SP] – 4 (Even)
[SP] – 3 (Odd)
[SP] – 2 (Even)
[SP] – 1 (Odd)
[SP]
(2) SP contains odd number
[SP] – 5 (Even)
[SP] – 4 (Odd)
[SP] – 3 (Even)
[SP] – 2 (Odd)
[SP] – 1 (Even)
[SP]
NOTE:
Figure 9.4.3.2. Operation of Saving Register
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Address
Stack
PC
FLG
FLG
H
(Even)
Address
Stack
PC
FLG
FLG
H
(Odd)
1. [SP] denotes the initial value of the SP when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
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Sequence in which order
registers are saved
PC
L
(2) Saved simultaneously,
M
L
(1) Saved simultaneously,
PC
H
Finished saving registers
in two operations.
Sequence in which order
registers are saved
PC
(3)
L
M
(4)
L
(1)
PC
(2)
H
Finished saving registers
in four operations.
(1)
all 16 bits
all 16 bits
Saved, 8 bits at a time
9. Interrupt
(1)
,
is even, the FLG
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