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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
Peripheral Clock Select Register
b7
b6
b5
b4
0 0
0 0 0
NOTE:
1. Write to this register after setting the PRC0 bit in PRCR register to 1 (write enable).
Processeor Mode Register 2
b7
b6
b5
NOTES:
1. Write to this register after setting the PRC1 bit in the PRCR register to 1 (write enable).
2. The PM20 bit becomes effective when PLC07 bit in the PLC0 register is set to 1 (PLL on). Change the PM20
bit when the PLC07 bit is set to 0 (PLL off). Set the PM20 bit to 0 (2 waits) when PLL clock > 16MHz.
3. Once this bit is set to 1, it cannot be cleared to 0 by program.
4. Writting to the following bits has no effect when the PM21 bit is set to 1:
Do not execute WAIT instruction when the PM21 bit is set to 1.
5. Setting the PM22 bit to 1 results in the following conditions:
•
The on-chip oscillator continues oscillating even if the CM21 bit in the CM2 register is set to "0" (main clock or
PLL clock) (system clock of count source selected by the CM21 bit is valid)
• The on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the watchdog timer
count source.
• The CM10 bit in the CM1 register cannnot be written. (Writing 1 has no effect, stop mode is not entered.)
• The watchdog timer does not stop in wait mode.
6. For NMI function, the PM24 bit must be set to 1(NMI function). Once this bit is set to 1, it cannot be set to 0 by
program.
7. SD input is valid regardless of the PM24 setting.
Figure 7.6. PCLKR Register and PM2 Register
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
6
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
(1)
Symbol
b3
b2
b1
b0
PCLKR
Bit Symbol
Timers A, B clock select bit
(Clock source for the timers A,
PCLK0
B, the timer S, the dead timer,
SI/O3, SI/O4 and multi-master
2
I
C bus)
SI/O clock select bit
PCLK1
(Clock source for UART0 to
UART2)
Reserved bit
(b4-b2)
Clock output function
PCLK5
expansion select bit
Reserved bit
(b7-b6)
(1)
b4
b3
b2
b1
b0
Symbol
0
PM2
Bit Symbol
Specifying wait when
PM20
accessing SFR (2)
System clock protective
PM21
bit (3,4)
WDT count source
PM22
protective bit
Reserved bit
(b3)
P8
PM24
Nothing is assigned. When write, set to 0.
(b7-b5)
When read, thecontent is undefined
CM02 bit in the CM0 register
CM05 bit in the CM0 register (main clock is not halted)
CM07 bit in the CM0 register (CPU clock source does not change)
CM10 bit in the CM1 register (stop mode is not entered)
CM11 bit in the CM1 register (CPU clock source does not change)
CM20 bit in the CM2 register (oscillation stop, re-oscillation detection function settings do not change)
All bits in the PLC0 register (PLL frequency synthesizer setting do not change)
page 43
f o
3
2
9
6
C
2 /
6
) T
Address
After Reset
025E
00000011
16
Bit Name
0: f
1: f
0: f
1: f
Set to 0
Refer to Table 7.5.3.1
Set to 0
Address
After Reset
001E
XXX00000
16
Bit Name
0: 2 waits
1: 1 wait
0: Clock is protected by PRCR
register
1: Clock modification disabled
0: CPU clock is used for the
watchdog timer count source
1: On-chip oscillator clock is used
(3,5)
for the watchdog timer count
source
Set to 0
8
0: P
/NMI configuration bit(6,7)
5
1: NMI function
7. Clock Generation Circuit
2
Function
2
1
SIO
2
SIO
1
2
Function
RW
RW
RW
RW
RW
function (NMI disabled)
5
RW
RW
RW
RW
RW
RW
RW
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