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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
6
Table 13.1.3.2. Registers to Be Used and Settings in I
Register
Bit
U2TB
0 to 7
(1)
U2RB
0 to 7
8
(1)
ABT
OER
U2BRG 0 to 7
U2MR
SMD2 to SMD0
CKDIR
(1)
IOPOL
U2C0
CLK1, CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
U2C1
TE
TI
RE
RI
U2IRS
U2RRM,
U2LCH, U2ERE
U2SMR IICM
ABC
BBS
3 to 7
U2SMR2 IICM2
CSC
SWC
ALS
STAC
SWC2
SDHI
7
U2SMR3 0, 2, 4 and NODC Set to "0"
CKPH
DL2 to DL0
NOTE:
1. Not all register bits are described above. Set those bits to "0" when writing to the registers in I
mode.
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
6
Master
Set transmission data
Reception data can be read
ACK or NACK is set in this bit
Arbitration lost detection flag
Overrun error flag
Set a transfer rate
Set to '010
'
2
Set to "0"
Set to "0"
Select the count source for the U2BRG
register
Invalid because CRD = 1
Transmit buffer empty flag
Set to "1"
Set to "1"
Set to "0"
Set to "1"
Set this bit to "1" to enable transmission
Transmit buffer empty flag
Set this bit to "1" to enable reception
Reception complete flag
Invalid
Set to "0"
Set to "1"
Select the timing at which arbitration-lost Invalid
is detected
Bus busy flag
Set to "0"
Refer to Table 13.1.3.4 I
Set this bit to "1" to enable clock
synchronization
Set this bit to "1" to have SCL
fixed to "L" at the falling edge of the 9th
bit of clock
Set this bit to "1" to have SDA
stopped when arbitration-lost is detected
Set to "0"
Set this bit to "1" to have SCL
forcibly pulled low
Set this bit to "1" to disable SDA
Set to "0"
Refer to Table 13.1.3.4 I
Set the amount of SDA
page 160
f o
3
2
9
C
2 /
6
) T
2
C bus Mode (1) (Continued)
Function
2
C bus Mode Functions
output
2
output
2
output
2
output
2
2
C bus Mode Functions
digital delay
2
Slave
Set transmission data
Reception data can be read
ACK or NACK is set in this bit
Invalid
Overrun error flag
Invalid
Set to '010
'
2
Set to "1"
Set to "0"
Invalid
Invalid because CRD = 1
Transmit buffer empty flag
Set to "1"
Set to "1"
Set to "0"
Set to "1"
Set this bit to "1" to enable transmission
Transmit buffer empty flag
Set this bit to "1" to enable reception
Reception complete flag
Invalid
Set to "0"
Set to "1"
Bus busy flag
Set to "0"
2
Refer to Table 13.1.3.4 I
C bus Mode Functions
Set to "0"
Set this bit to "1" to have SCL
fixed to "L" at the falling edge of the 9
bit of clock
Set to "0"
Set this bit to "1" to initialize UART2 at
start condition detection
Set this bit to "1" to have SCL
forcibly pulled low
Set this bit to "1" to disable SDA
Set to "0"
Set to "0"
2
Refer to Table 13.1.3.4 I
C bus Mode Functions
Set the amount of SDA
digital delay
2
13. Serial I/O
output
2
th
output
2
output
2
2
C bus
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