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8. If the CPU reads the A/D register i (i = 0 to 7) at the same time the conversion result is stored in the A/
D register i after completion of A/D conversion, an incorrect value may be stored in the A/D register i.
This problem occurs when a divide-by-n clock derived from the main clock or a subclock is selected for
CPU clock.
• When operating in one-shot mode, single-sweep mode, simultaneous sample sweep mode, delayed
trigger mode 0 or delayed trigger mode 1
Check to see that A/D conversion is completed before reading the target A/D register i. (Check the IR
bit in the ADIC register to see if A/D conversion is completed.)
• When operating in repeat mode or repeat sweep mode 0 or 1
Use the main clock for CPU clock directly without dividing it.
9. If A/D conversion is forcibly terminated while in progress by setting the ADST bit in the ADCON0
register to "0" (A/D conversion halted), the conversion result of the A/D converter is indeterminate. The
contents of A/D register i irrelevant to A/D conversion may also become indeterminate. If while A/D
conversion is underway the ADST bit is cleared to "0" in a program, ignore the values of all A/D register
i.
10.When setting the ADST bit in the ADCON register to "0" to terminate a conversion forcefully by the
program in single sweep conversion mode, A/D delayed trigger mode 0 and A/D delayed trigger mode
1 during A/D conversion operation, the A/D interrupt request may be generated. If this causes a prob-
lem, set the ADST bit to "0" after the interrupt is disabled.
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19. Usage Notes
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