Table of Contents
Advertisement
M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
Transfer clock
UiC1 register
"1"
TE bit
"0"
UiC1 register
TI bit
"1"
"0"
"H"
CTSi
"L"
TxDi
UiC0 register
"1"
TXEPT bit
"0"
"1"
SiTIC register
IR bit
"0"
The above timing diagram applies to the case where the register bits are set
as follows:
• Set the PRYE bit in the UiMR register to "1" (parity enabled)
• Set the STPS bit in the UiMR register to "0" (1 stop bit)
• Set the CRD bit in the UiC0 register to "0" (CTS/RTS enabled),
the CRS bit to "0" (CTS selected)
• Set the UiIRS bit to "1" (an interrupt request occurs when transmit completed):
U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Transfer clock
"1"
UiC1 register
TE bit
"0"
"1"
UiC1 register
TI bit
"0"
TxDi
"1"
UiC0 register
TXEPT bit
"0"
"1"
SiTIC register
IR bit
"0"
The above timing diagram applies to the case where the register bits are set
as follows:
• Set the PRYE bit in the UiMR register to "0" (parity disabled)
• Set the STPS bit in the UiMR register to "1" (2 stop bits)
• Set the CRD bit in the UiC0 register to "1"(CTS/RTS disabled)
• Set the UiIRS bit to "0" (an interrupt request occurs when transmit buffer
becomes empty):
U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
Figure 13.1.2.1. Typical transmit timing in UART mode (UART0, UART1)
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
6
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
The transfer clock stops momentarily as CTSi is "H" when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTSi changes to "L".
Tc
Write data to the UiTB register
Start
bit
ST
D
D
D
D
D
0
2
3
1
4
Tc
Write data to the UiTB register
Start
bit
ST
D
D
D
D
D
0
1
2
3
4
Cleared to "0" when interrupt request is accepted, or cleared to "0" in a program
page 153
f o
3
2
9
6
C
2 /
6
) T
Transferred from UiTB register to UARTi transmit register
Parity
Stop
bit
bit
D
P
SP
ST
D
D
D
D
D
7
0
5
6
1
Cleared to "0" when interrupt request is accepted, or cleared to "0" in a program
Tc = 16 (n + 1) / fj or 16 (n + 1) / f
fj : frequency of UiBRG count source (f
f
: frequency of UiBRG count source (external clock)
EXT
n : value set to UiBRG
i: 0 to 2
Transferred from UiTB register to UARTi
transmit register
Stop
Stop
bit
bit
D
D
D
D
SP
SP
ST
D
D
5
6
7
8
0
1
Tc = 16 (n + 1) / fj or 16 (n + 1) / f
fj : frequency of UiBRG count source (f
f
: frequency of UiBRG count source (external clock)
EXT
n : value set to UiBRG
i: 0 to 2
Stopped pulsing
because the TE bit
= "0"
D
D
D
P SP
D
D
2
3
7
4
5
6
EXT
1SIO
D
D
D
D
D
D
D
SPSP
2
3
4
5
6
7
8
EXT
1SIO
13. Serial I/O
ST
D
D
0
1
, f
, f
, f
)
2SIO
8SIO
32SIO
ST
D
D
0
1
, f
, f
, f
)
2SIO
8SIO
32SIO
Advertisement
Table of Contents
