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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
6
SDA2
Noise
Filter
SCL2
Noise
Filter
This diagram applies to the case where the SMD2 to SMD0 bits in the the U2MR register is set to "010
register is set to "1".
IICM
IICM2, SWC, ALS, SWC2, SDHI : Bits in the U2SMR2
STSPSEL, ACKD, ACKC
NOTE:
1. If the IICM bit is set to "1", the pin can be read even when the PD7_1 bit is set to "1" (output mode).
2
Figure 13.1.3.1. I
C bus Mode Block Diagram
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
6
STSPSEL=1
Delay
circuit
STSPSEL=0
ACKC=1
ACKC=0
SDHI
ACKD bit
D
Arbitration
Q
T
Start condition
detection
Stop condition
detection
Falling edge
detection
Port register
IICM=0
R
(1)
I/O port
Q
Internal clock
STSPSEL=0
UART2
IICM=1
STSPSEL=1
External
clock
: Bit in the U2SMR
: Bits in the U2SMR4
page 159
f o
3
2
9
C
2 /
6
) T
Start and stop condition generation block
SDA
STSP
SCL
STSP
Transmission
register
UART2
ALS
Reception register
UART2
S
Bus
Q
busy
R
D
Q
T
D
Q
T
9th bit
SWC2
CLK
control
UART2
9th bit falling edge
R
S
SWC
DMA0, DMA1 request
IICM2=1
UART2 transmit,
NACK interrupt
request
IICM=1 and
IICM2=0
DMA0
IICM2=1
UART2 receive,
ACK interrupt request,
DMA1 request
IICM=1 and
IICM2=0
NACK
ACK
Start/stop condition detection
interrupt request
" and the IICM bit in the U2SMR
2
13. Serial I/O
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