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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
6
Three-phase output buffer register(i=0,1)
b7
b5
b4
b3
NOTE:
1. The IDB0 and IDB1 register values are transferred to the three-phase shift register by a transfer trigger. The value
written to the IDB0 register aftera transfer trigger represents the output signal of each phase, and the next value written
to the IDB1 register at the falling edge of the timer A1, A2 or A4 one-shot pulse represents the output signal of each
phase.
Dead time timer
b7
b6
b5
b4
b3
NOTES:
1. Use MOV instruction to write to this register.
2. Effective when the INV15 bit is set to "0" (dead time timer enable). If the INV15 bit is set to "1", the dead time timer is
disabled and has no effect.
Timer B2 Interrupt Occurrences Frequency Set Counter
b7 b6 b5
b4
NOTE:
1. Use MOV instruction to write to this register.
If the INV01 bit is set to "1", make sure the TB2S bit also is set to "0" (timer B2 count stopped) when writing to
this register. If the INV01 bit is set to "0", although this register can be written even when the TB2S bit is set to
"1" (timer B2 count start), do not write synchronously with a timer B2 underflow.
Figure 12.3.4. IDB0 Register, IDB1Register, DTT Register, and ICTB2 Register
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
6
b2
b1
b0
Symbol
IDB0
IDB1
Bit symbol
Bit name
DUi
U phase output buffer i
DUBi
U phase output buffer i
DVi
V phase output buffer i
DVBi
V phase output buffer i
DWi
W phase output buffer i
DWBi
W phase output buffer i
Nothing is assigned. When write, set to "0". When read,
(b7-b6)
these contents are "0".
(1, 2)
b2
b1
b0
Symbol
DTT
Assuming the set value = n, upon a start trigger the timer starts
counting the count souce selected by the INV12 bit and stops
after counting it n times. The positive or negative phase
whichever is going from an inactive to an active level changes
at the same time the dead time timer stops.
b3
b0
Symbol
ICTB2
If the INV01 bit is "0" (ICTB2 counter counted every
time timer B2 underflows), assuming the set value
= n, a timer B2 interrupt is generated at every níth
occurrence of a timer B2 underflow.
If the INV01 bit is "1" (ICTB2 counter count timing
selected by the INV00 bit), assuming the set value
= n, a timer B2 interrupt is generated at every níth
occurrence of a timer B2 underflow that meets the
condition selected by the INV00 bit.
Nothing is assigned. When write, set to "0". When read, its content is
indeterminate.
page 121
f o
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2
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) T
(1)
Address
034A
16
034B
16
Write the output level
0: Active level
1: Inactive level
When read, these bits show the three-phase
output shift register value.
Address
034C
16
Function
Address
After Reset
034D
Indeterminate
16
Function
(1)
When reset
00111111
2
00111111
2
Function
When reset
Indeterminate
Setting range
1 to 255
RW
Setting Range
1 to 15
WO
12. Timer
RW
RW
RW
RW
RW
RW
RW
RO
RW
WO
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