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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
6
A/D trigger control register (1)
b7
b6
b5
b4
b3
1
NOTE:
1. If ADTRGCON reigster is rewritten during A/D conversion, the conversion result will be indeterminate.
Figure 14.1.7.5 ADTRGCON Register in Delayed Trigger Mode 0
Table 14.1.7.2 Trigger Select Bit Setting in Delayed Trigger Mode 0
TRG
TRG1
0
0
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
6
b2
b1
b0
Symbol
1
1
1
ADTRGCON
Bit symbol
A/D Operation Mode
SSE
Select Bit 2
A/D Operation Mode
DTE
Select Bit 3
AN0 Trigger Select Bit
HPTRG0
AN1 Trigger Select Bit
HPTRG1
Nothing is assigned. When write, set to "0".
(b7-b4)
When read, its content is "0".
HPTRG1
HPTRG0
1
1
Timer B0, B1 underflow
page 204
f o
3
2
9
C
2 /
6
) T
Address
After reset
03D2
00
16
Bit name
Simultaneous sample sweep mode or
delayed trigger mode 0,1
Delayed trigger mode 0, 1
Refer to Table 14.1.7.2 Trigger Select
Bit Setting in Delayed Trigger Mode 0
Refer to Table 14.1.7.2 Trigger Select
Bit Setting in Delayed Trigger Mode 0
Trigger
16
Function
RW
RW
RW
14. A/D Converter
RW
RW
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