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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
6
Priority level of each interrupt
Timer B2
Timer B0
Timer A3
Timer A1
Timer A2
UART1 reception
UART0 reception
UART2 reception, ACK2
A/D conversion
UART 2 bus collision
Timer A0
UART1 transmission
UART0 transmission
UART2 transmission, NACK2
Key input interrupt
Address match
Watchdog timer
Oscillation stop and
re-oscillation detection
Voltage down detection
Figure 9.5.1.1. Interrupts Priority Select Circuit
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
Level 0 (initial value)
INT1
INT3
INT2
INT0
Timer B1
Timer A4
DMA1
INT5
DMA0
INT4
IPL
I flag
DBC
NMI
page 75
f o
3
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) T
Highest
Priority of peripheral function interrupts
(if priority levels are same)
Lowest
Interrupt request level resolution output to clock
generating circuit (Fig.7.1.)
Interrupt
request
accepted
9. Interrupt
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