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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
6
0 0 F 0 0 0
1 6
B l o c k B : 2 K b y t e s (2)
0 0 F 7 F F
1 6
0 0 F 8 0 0
1 6
B l o c k A : 2 K b y t e s (2)
0 0 F F F F
1 6
0 F A 0 0 0
1 6
B l o c k 2 : 8 K b y t e s (5)
0 F B F F F
1 6
0 F C 0 0 0
1 6
B l o c k 1 : 8 K b y t e s (3)
0 F D F F F
1 6
0 F E 0 0 0
1 6
B l o c k 0 : 8 K b y t e s (3)
0 F F F F F
1 6
Figure 17.2.3. Flash Memory Block Diagram (ROM capacity 24K byte)
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
6
U s e r R O M a r e a
page 234
f o
3
2
9
C
2 /
6
) T
NOTES:
1. To specify a block, use the maximum even address in the block.
2. Blocks A and B are enabled to use when the PM10 bit in the PM1
register is set to "1".
3. Blocks 0 and 1 are enabled for programs and erases when the
FMR02 bit in the FMR0 register is set to "1" and the FMR16 bit in
the FMR1 register is set to "1". (CPU rewrite mode only)
4. The boot ROM area is reserved. Do not access.
5. Blocks 2 are enabled for programs and erases when the FMR16 bit
in the FMR1 register is set to "1". (CPU rewrite mode only)
0 F F 0 0 0
1 6
0 F F F F F
1 6
17. Flash Memory Version
4 K b y t e s (4)
B o o t R O M a r e a
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