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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
6
A/D trigger control register
b7
b6
b5
b4
b3
0
NOTE:
1. If ADTRGCON register is rewritten during A/D conversion, the conversion result will be indeterminate.
Figure 14.1.6.3 ADTRGCON Register in Simultaneous Sample Sweep Mode
Table 14.1.6.2 Trigger Select Bit Setting in Simultaneous Sample Sweep Mode
TRG
TRG1
HPTRG0
-
0
-
1
1
0
1
1
NOTE:
1. A count can be started for Timer B2, Timer B2 interrupt generation frequency setting counter underflow or
the INT5 pin falling edge as count start conditions of Timer B0.
2. Select Timer B2 or Timer B2 interrupt generation frequency setting counter using the TB2SEL bit in the
TB2SC register.
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
6
(1)
b2
b1
b0
Symbol
0
1
ADTRGCON
Bit symbol
A/D Operation Mode
SSE
Select Bit 2
A/D Operation Mode
DTE
Select Bit 3
AN0 Trigger Select Bit
HPTRG0
AN1 Trigger Select Bit
HPTRG1
Nothing is assigned. When write, set to "0".
(b7-b4)
When read, its content is "0".
TRIGGER
Software trigger
-
1
Timer B0 underflow (1)
0
AD
TRG
Timer B2 or Timer B2 interrupt generation frequency
0
setting counter underflow (2)
page 198
f o
3
2
9
C
2 /
6
) T
Address
After reset
03D2
16
Bit name
1 : Simultaneous sample sweep mode
or delayed trigger mode 0, 1
0 : Any mode other than delayed trigger
mode 0,1
Refer to Table 14.1.6.2 Trigger Select
Bit Setting in Simultaneous Sample
Sweep Mode
Set to "0" in simultaneous sample
sweep mode
00
16
Function
14. A/D Converter
RW
RW
RW
RW
RW
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