Table of Contents
Advertisement
M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
6
Timer B2 special mode register
b7
b6
b5
b4
b3
b2
0
0
NOTES:
1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enabled).
2. If the INV11 bit is "0" (three-phase mode 0) or the INV06 bit is "1" (triangular wave modulation mode), set this bit to
"0" (timer B2 underflow).
3. When setting the IVPCR1 bit to "1" (three-phase output forcible cutoff by SD pin input enabled), Set the PD8_5 bit to
"0" (= input mode).
4. Related pins are U(P8
pin and set the IVPCR1 bit to 0 after forcible cutoff, pins U, U, V, V, W, and W are exit from the high-impedance state.
If a low-level ("L") signal is applied to the SD pin, three-phase motor control timer output will be disabled (INV03=0).
At this time, when the IVPCR1 bit is 0, pins U, U, V, V, W, and W become programmable I/O ports. When the IVPCR1
bit is set to 1, pins U, U, V, V, W, and W are placed in a high-impedance state regardless of which function of those
pins is used.
5. When this bit is used in delayed trigger mode 0, set the TB0EN and TB1EN bits to "1"(A/D trigger mode).
6. When setting the TB2SEL bit to "1" (underflow of TB2 interrupt generation frequency setting counter[ICTB2]), Set the
INV02 bit to "1" (three-phase motor control timer function).
7. Refer to 16.6 Digital Debounce function for SD input.
Figure 14.5 TB2SC Register
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
6
(1)
b1
b0
Symbol
Address
TB2SC
039E
Bit symbol
Timer B2 Reload Timing
PWCOM
Switch Bit
Three-Phase Output Port
IVPCR1
SD Control Bit 1
Timer B0 Operation Mode
TB0EN
Select Bit
Timer B1 Operation Mode
TB1EN
Select Bit
TB2SEL
Trigger Select Bit
Reserved bits
(b6-b5)
Nothing is assigned. When write, set to "0".
(b7)
When read, its content is "0".
), U(P8
), V(P7
), V(P7
0
1
2
page 185
f o
3
2
9
C
2 /
6
) T
After reset
X0000000
16
Bit name
0 : Timer B2 underflow
(2)
1 : Timer A output at odd-numbered
0 : Three-phase output forcible cutoff
by SD pin input (high impedance)
disabled
(3, 4, 7)
1 : Three-phase output forcible cutoff
by SD pin input (high impedance)
enabled
0 : Other than A/D trigger mode
1 : A/D trigger mode
0 : Other than A/D trigger mode
1 : A/D trigger mode
(6)
0 : TB2 interrupt
1 : Underflow of TB2 interrupt
generation frequency setting counter [ICTB2]
Must set to "0"
), W(P7
), W(P7
). When a high-level ("H") signal is applied to the SD
3
4
5
2
Function
(5)
(5)
14. A/D Converter
RW
RW
RW
RW
RW
RW
RW
Advertisement
Table of Contents
