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14.1.8 Delayed Trigger Mode 1
In delayed trigger mode 1, analog voltages applied to the selected pins are converted one-by-one to a
digital code. When the input of the AD
conversion is started. After completing the AN
until the second AD
The single sweep conversion of the pins after the AN
trigger mode 1 specifications. Figure 14.1.8.1 shows the operation example of delayed trigger mode 1.
Figure 14.1.8.2 to Figure 14.1.8.3 show each flag operation in the ADSTAT0 register that corresponds to
the operation example. Figure 14.1.8.4 shows the ADCON0 to ADCON2 registers in delayed trigger
mode 1. Figure 14.1.8.5 shows the ADTRGCON register in delayed trigger mode 1 and Table 15.1.8.2
shows the trigger select bit setting in delayed trigger mode 1.
Table 14.1.8.1 Delayed Trigger Mode 1 Specifications
Item
Function
A/D Conversion Start
Condition
A/D Conversion Stop
Condition
Interrupt Request
Generation Timing
Analog Input Pin
Readout of A/D Conversion Result
NOTES:
1. Do not generate the next AD
complete A/D conversion. When an AD
is ignored. The falling edge of AD
considered to be the next AN0 pin conversion start condition.
___________
pin falling edge is detected synchronized with the operation clock φ
2. The AD
TRG
falling edge is generated in shorter periods than φ
not generate the AD
3. Do not write "1" (A/D conversion started) to the ADST bit in delayed trigger mode 1. When write "1", unexpected
interrupts may be generated.
4. AN
to AN
can be used in the same way as AN
30
32
group.
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TRG
pin falling edge is generated. When the second AD
TRG
The SCAN1 to SCAN0 bits in the ADCON1 register and ADGSEL1 to ADGSEL0 bits
in the ADCON2 register select pins. Analog voltages applied to the selected pins are
converted one-by-one to a digital code. At this time, the AD
falling edge starts AN
conversion of the pins after AN
AN
pin conversion start condition
0
The AD
pin input changes state from "H" to "L" (falling edge)
TRG
AN
pin conversion start condition
1
The AD
pin input changes state from "H" to "L" (falling edge)
TRG
•When the second AD
conversion of the AN
falling edge. The conversion of AN
conversion is completed.
•When the AD
sion of pins after the AN
•A/D conversion completed
•Set the ADST bit to "0" (A/D conversion halted)
Single sweep conversion completed
Select from AN
AN
to AN
(8 pins)
0
7
Readout one of the AN0 to AN7 registers that corresponds to the selected pins
___________
pin falling edge after the AN1 pin conversion is started until all selected pins
TRG
___________
TRG
___________
pin, which was input after all selected pins complete A/D conversion, is
TRG
___________
pin falling edge in shorter periods than φ
TRG
page 205
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pin (falling edge) changes state from "H" to "L", a single sweep
pin conversion, the AN
0
pin is restarted. Table 14.1.8.1 shows the delayed
1
Specification
pin conversion and the second AD
0
pin
1
(2)
pin falling edge is generated during or after A/D
TRG
pin, input voltage of AN
0
and the rest of the sweep starts when AN
1
pin falling edge is generated again during single sweep conver
TRG
pin, the conversion is not affected
1
to AN
(2 pins), AN
to AN
0
1
0
(4)
pin falling edge is generated again during A/D conversion, its trigger
___________
, the second AD
AD
TRG
AD
to AN
. However, all input pins need to belong to the same
0
7
pin is not sampled and converted
1
falling edge is generated,
TRG
pin
TRG
pin falling edge starts
TRG
(1)
pin is sampled at the time of AD
1
(3)
(4 pins), AN
to AN
3
0
5
. Therefore, when the AD
AD
pin falling edge may not be detected. Do
.
14. A/D Converter
TRG
0
(6 pins) and
___________
pin
TRG
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