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6
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o r
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6
Table 13.1.4.2. Registers to Be Used and Settings in Special Mode 2
Register
Bit
(1)
U2TB
0 to 7
(1)
U2RB
0 to 7
OER
U2BRG
0 to 7
(1)
U2MR
SMD2 to SMD0
CKDIR
IOPOL
U2C0
CLK1, CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
U2C1
TE
TI
RE
RI
U2IRS
U2RRM,
U2LCH, U2ERE
U2SMR
0 to 7
U2SMR2
0 to 7
U2SMR3
CKPH
NODC
0, 2, 4 to 7
U2SMR4
0 to 7
NOTE:
1. Not all bits in the register are described above. Set those bits to "0" when writing to the registers in
Special Mode 2.
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
C
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6
, A
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M
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6
Set transmission data
Reception data can be read
Overrun error flag
Set a transfer rate
Set to '001
'
2
Set this bit to "0" for master mode or "1" for slave mode
Set to "0"
Select the count source for the U2BRG register
Invalid because CRD = 1
Transmit register empty flag
Set to "1"
Select TxD2 pin output format
Clock phases can be set in combination with the CKPH bit in the U2SMR3
register
Set to "0"
Set this bit to "1" to enable transmission
Transmit buffer empty flag
Set this bit to "1" to enable reception
Reception complete flag
Select UART2 transmit interrupt cause
Set to "0"
Set to "0"
Set to "0"
Clock phases can be set in combination with the CKPOL bit in the U2C0 register
Set to "0"
Set to "0"
Set to "0"
page 170
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Function
13. Serial I/O
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