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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
6
NMI Digital Debounce Register
b7
NOTES:
1. Set the PACR register by the next instruction after setting the PRC2 bit in the PRCR register to "1"(write
enable).
2. When using the NMI interrupt to exit from stop mode, set the NDDR registert to "FF
stop mode.
P1
Digital Debounce Register
7
b7
NOTE:
1. When using the INT5 interrupt to exit from stop mode, set the P17DDR registert to "FF
stop mode.
Figure 16.6.1. NDDR and P17DDR Registers
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
6
(1,2)
b0
Symbol
NDDR
If the set value =n,
- n = 0 to FE
; a signal with pulse width, greater than
16
(n+1)/f8, is input into NMI / SD
- n = FF
; the digital debounce filter is disabled and all
16
signals are input
(1)
Symbol
b0
P17DDR
If the set value =n,
- n = 0 to FE
; a signal with pulse width, greater than
16
(n+1)/f8, is input into INPC17/ INT5
- n = FF
; the digital debounce filter is disabled and all
16
signals are input
page 227
f o
3
2
9
C
2 /
6
) T
Address
After Reset
033E
FF
16
16
Function
Address
After Reset
033F
FF
16
16
Function
16. Programmable I/O Ports
Setting Range
RW
00
to FF
16
16
RW
" before entering
16
Setting Range
RW
00
to FF
16
16
RW
" before entering
16
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