Line Buffer; Cursor Control Logic; Frame Rate Control (Frc) - Motorola DragonBall MC68328 User Manual

LCD Controller
Address
Data
68EC000
BR
Core
BG
SIM28
OE
CS
System
Memory

4.1.3 Line Buffer

The line buffer collects display data from system memory during DMA cycles, and outputs
it to the cursor-logic block. The input is synchronized with the fast DMA clock, while the out-
put is synchronized to the relatively slow LCD pixel clock.

4.1.4 Cursor Control Logic

The cursor control logic (when enabled) generates a block-shaped cursor on the display
screen. Users can adjust the cursor height and width to any number between 1 to 31. The
cursor can be full black or reversed video, and the blinking rate is adjustable when the blink-
enable bit is on.

4.1.5 Frame Rate Control (FRC)

The frame rate control (FRC) is used primarily for gray-scale display and can generate up
to 4 gray levels from the choice of 7 density levels (0, 1/4, 5/16, 1/2, 11/16, 3/4, 1 as in Table
4-3). The density level corresponds to the number of times the pixel is being turned on when
the display is refreshed frame by frame. Because the crystal formulations and driving volt-
age may vary, the visual gray quality can be tuned by programming the gray palette-map-
ping register (GPMR) to obtain the best effect.
Because blinking or flickering will occur if all LCD pixel cells are synchronized, it is essential
to program two 4-bit numbers, namely Xoff and Yoff in the FRC offset register (FOSR), to
minimize flickering. As a general rule, select odd numbers that differ by 2. The optimal offset
4-2 MC68328 DRAGONBALL PROCESSOR USER'S MANUAL
System
Clock
(fast)
MPU
Interface
Registers
Screen
DMA
Line Buffer
Figure 4-1. System Block Diagram of LCDC
LCD
Clock
(slow)
LCDC
LCD
Interface
Frame
Rate
Control
Cursor
Logic
LCD Driver
MOTOROLA