ST STM32F205 series Reference Manual page 1371

RM0033
Date
02-May-2018
Table 224. Document revision history (continued)
Version
USB OTG_HS (continued)
Changed NPTXFD access type in
transmit FIFO size/Endpoint 0 transmit FIFO size register
(OTG_HS_GNPTXFSIZ/OTG_HS_TX0FSIZ).
Updated Section : OTG_HS nonperiodic transmit FIFO/queue status
register (OTG_HS_GNPTXSTS)
core configuration register (OTG_HS_GCCFG)
Suppressed OTG_HS_GI2CCTL register
Updated FRIVL definition in
register (OTG_HS_HFIR).
Changed PTXFSAVL access type to 'r' in
frame number/frame time remaining register (OTG_HS_HFNUM)
Renamed bit 2 name into AHBERRM and definition updated in
Section : OTG_HS host channel-x interrupt mask register
(OTG_HS_HCINTMSKx) (x = 0..11, where x =
Updated bit 7:9 definition in
register (OTG_HS_DCTL).
Added NAKM and AHBERRM bits in
endpoint common interrupt mask register
Added NYETMSK, NAKMSK, BERRM, STSPHSRXM and
AHBERRM bits in
interrupt mask register
Replaced DWORDS by words in
threshold control register
8
Added AHBERRM in
(continued)
interrupt register
Updated STALL bit definition in
control register (OTG_HS_DOEPCTLx) (x = 1..3, where x =
Endpoint_number).
Removed BERR bit and added BNA, INEPNM and AHBERR bits in
Section : OTG_HS device endpoint-x interrupt register
(OTG_HS_DIEPINTx) (x = 0..7, where x =
Added NAK, BERR, OUTPKTERR and AHBERR bits in
OTG_HS device endpoint-x interrupt register (OTG_HS_DOEPINTx)
(x = 0..7, where x =
FSMC
Updated Section 31.3: AHB
Modified Figure 411: Multiplexed write
Added note related to the hold phase delay below
NAND/PC Card controller timing for common memory
Updated Section 31.6.5: NAND Flash prewait
Updated note related to IRS and IFS bits in FSMC_SR.
Updated BUSTURN bitfield description in
timing registers 1..4 (FSMC_BWTR1..4)
chip-select timing registers 1..4
Updated MEMHOLDx in
(FSMC_PMEM2..4)
registers 2..4
RM0033 Rev 8
Changes
Section : OTG_HS nonperiodic
and
Section : OTG_HS Host frame interval
Section : OTG_HS device control
Section : OTG_HS device IN
Section : OTG_HS device OUT endpoint common
(OTG_HS_DOEPMSK).
Section : OTG_HS Device
(OTG_HS_DTHRCTL).
Section : OTG_HS device each in endpoint-1
(OTG_HS_DIEPEACHMSK1).
Section : OTG_HS device endpoint-x
Endpoint_number).
interface.
(FSMC_BTR1..4).
Common memory space timing register 2..4
and ATTHOLD in
(FSMC_PATT2..4).
Revision history
Section : OTG_HS general
reset value.
Section : OTG_HS host
Channel_number).
(OTG_HS_DIEPMSK).
Endpoint_number).
Section :
accesses.
Figure 417:
access.
functionality.
SRAM/NOR-Flash write
and SRAM/NOR-Flash
Attribute memory space timing
1371/1378
1372