Table 3-2 Burst Types; Figure 3-3 Sequential Access Cycles; Internal Cycles - ARM ARM7TDMI Technical Reference Manual

3.3.3

Internal cycles

ARM DDI 0210C
The possible burst types are listed in Table 3-2.
Burst type Address increment
Word read 4 bytes
Word write 4 bytes
Halfword read 2 bytes
All accesses in a burst are of the same data width, direction, and protection type. For
more details, see Addressing signals on page 3-11.
Memory systems can often respond faster to a sequential access and can require a
shorter access time compared to a nonsequential access. An example of a burst access
is shown in Figure 3-3.
MCLK
A[31:0]
nMREQ
SEQ
nRAS
nCAS
D[31:0]
During an internal cycle, the ARM7TDMI processor does not require a memory access,
as an internal function is being performed, and no useful prefetching can be performed
at the same time.
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Cause
ARM7TDMIcore code fetches, or LDM instruction
STM instruction
Thumb code fetches
N-cycle
a

Figure 3-3 Sequential access cycles

Memory Interface

Table 3-2 Burst types

S-cycle S-cycle
a+4 a+8
a+12
3-7