23.6.18 Acceptance Mask Select Register (AMSR)
This register selects masks (acceptance mask) for comparison between the receive message ID and the
message buffer (x) ID.
n Acceptance Mask Select Register (AMSR)
BYTE0
Address: 003C10
(CAN0)
H
Address: 003D10
(CAN1)
H
Read/write →
Initial value →
BYTE1
Address: 003C11
(CAN0)
H
Address: 003D11
(CAN1)
H
Read/write →
Initial value →
BYTE2
Address: 003C12
(CAN0)
H
Address: 003D12
(CAN1)
H
Read/write →
Initial value →
BYTE3
Address: 003C13
(CAN0)
H
Address: 003D13
(CAN1)
H
Read/write →
Initial value →
Note:
This register should be set when the message buffer (x) is invalid (BVALx of the message buffer
valid register (BVALR) = 0). Setting when the buffer is valid (BVALx = 1) may cause unnecessary
received messages to be stored.
CAN CONTROLLER
7
6
AMS3.1
AMS3.0
(R/W)
(R/W)
(X)
(X)
15
14
AMS7.1
AMS7.0
(R/W)
(R/W)
(X)
(X)
7
6
AMS11.1
AMS11.0
(R/W)
(R/W)
(X)
(X)
15
14
AMS15.1
AMS15.0
(R/W)
(R/W)
(X)
(X)
Table 23-7 Selection of Acceptance Mask
AMSx.1
AMSx.0
0
0
0
1
1
0
1
1
5
4
3
AMS2.1
AMS2.0
AMS1.1
(R/W)
(R/W)
(R/W)
(X)
(X)
(X)
13
12
11
AMS6.1
AMS6.0
AMS5.1
(R/W)
(R/W)
(R/W)
(X)
(X)
(X)
5
4
3
AMS9.1
AMS10.1
AMS10.0
(R/W)
(R/W)
(R/W)
(X)
(X)
(X)
13
12
11
AMS14.1
AMS14.0
AMS13.1
(R/W)
(R/W)
(R/W)
(X)
(X)
(X)
Acceptance Mask
Full-bit comparison
Full-bit mask
Acceptance mask register 0 (AMR0)
Acceptance mask register 1 (AMR1)
23-25
2
1
0
AMS1.0
AMS0.1
AMS0.0
(R/W)
(R/W)
(R/W)
(X)
(X)
(X)
10
9
8
AMS5.0
AMS4.1
AMS4.0
(R/W)
(R/W)
(R/W)
(X)
(X)
(X)
2
1
0
AMS9.0
AMS8.1
AMS8.0
(R/W)
(R/W)
(R/W)
(X)
(X)
(X)
10
9
8
AMS13.0
AMS12.1
AMS12.0
(R/W)
(R/W)
(R/W)
(X)
(X)
(X)
← Bit No.
← Bit No.
← Bit No.
← Bit No.