Table 8-9: Selection Of Pclk And Mclk In Swivelview Mode - Epson S1D13704 Technical Manual

Epson Research and Development
Vancouver Design Center
SwivelView
Mode Enable
(REG[1Bh] bit 7)
REG[1Ch] Line Byte Count Register for SwivelView Mode
Address = FFFCh
Line Byte Line Byte
Count bit 7 Count bit 6
bits 7-0
REG[1Eh] and REG[1Fh]
Hardware Functional Specification
Issue Date: 01/02/08

Table 8-9: Selection of PCLK and MCLK in SwivelView Mode

SwivelView
Mode Select
(REG[1Bh] bit 6)
0 X
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
Line Byte Line Byte
Count bit 5 Count bit 4
Line Byte Count Bits [7:0]
This register is the byte count from the beginning of one line to the beginning of the next
consecutive line (commonly called "stride" by programmers). This register may be used to
create a virtual image in SwivelView mode.
REG[1Eh] and REG[1Fh] are reserved for factory S1D13704 testing and should not be
written. Any value written to these registers may result in damage to the S1D13704 and/or
any panel connected to the S1D13704.
Pixel Clock (PCLK) Select
(REG[1Bh] bits [1:0]
Bit 1 Bit 0
X X
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
Where CLK is CLKI (REG[02h] bit 4 = 0) or CLKI/2 (REG[02h] bit 4 = 1)
Line Byte
Count bit 3
*
PCLK =
CLK See Reg[02h] bit 5
CLK
CLK/2
CLK/4
CLK/8
CLK/2
CLK/2
CLK/4
CLK/8
Line Byte Line Byte
1
Count bit 2 Count bit
Page 69
MCLK =
CLK
CLK/2
CLK/4
CLK/8
CLK
CLK
CLK/2
CLK/4
Read/Write
Line Byte
0
Count bit
S1D13704
X26A-A-001-04