Table 202. Power And Clock Gating Control And Status Registers - ST STM32F405 Reference Manual

USB on-the-go full-speed (OTG_FS)
...
Device IN Endpoint x
Device OUT Endpoint x
1. Where x is 3 in device mode and 7 in host mode.
Power and clock gating CSR map
There is a single register for power and clock gating. It is available in both host and device
modes.
Power and clock gating control register
Reserved
1270/1749
Table 201. Data FIFO (DFIFO) access register map (continued)
FIFO access register section
(1)
/Host OUT Channel x
(1)
/Host IN Channel x

Table 202. Power and clock gating control and status registers

Register name
RM0090 Rev 18
(1)
: DFIFO Write Access
(1)
: DFIFO Read Access
Acronym
OTG_FS_PCGCCTL 0xE00-0xE04
- 0xE05–0xFFF
RM0090
Address range
...
0xX000–0xXFFC
Offset address: 0xE00–0xFFF
Access
...
w
r