Figure 391. Updating Otg_Fs_Hfir Dynamically - ST STM32F405 Reference Manual

USB on-the-go full-speed (OTG_FS)
SOF
reload
OTG_FS_HFIR
write
OTG_FS_HFIR
value
Frame
timer
34.10 USB data FIFOs
The USB system features 1.25 Kbyte of dedicated RAM with a sophisticated FIFO control
mechanism. The packet FIFO controller module in the OTG_FS core organizes RAM space
into Tx-FIFOs into which the application pushes the data to be temporarily stored before the
USB transmission, and into a single Rx FIFO where the data received from the USB are
temporarily stored before retrieval (popped) by the application. The number of instructed
FIFOs and how these are organized inside the RAM depends on the device's role. In
peripheral mode an additional Tx-FIFO is instructed for each active IN endpoint. Any FIFO
size is software configured to better meet the application requirements.
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Figure 391. Updating OTG_FS_HFIR dynamically

Old OTG_FS_HIFR value
= 400 periods
400
...
RM0090 Rev 18
OTG_FS_HIFR value
= 450 periods+HIFR write latency
Latency
450
... ...
RM0090
New OTG_FS_HIFR value
= 450 periods
...
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