ST STM32F405 Reference Manual page 1305

RM0090
Bit 3 EERR: Erratic error
Bits 2:1 ENUMSPD: Enumerated speed
Bit 0 SUSPSTS: Suspend status
– When there is an activity on the USB data lines
– When the application writes to the Remote wakeup signaling bit in the OTG_FS_DCTL
OTG_FS device IN endpoint common interrupt mask register
(OTG_FS_DIEPMSK)
Address offset: 0x810
Reset value: 0x0000 0000
This register works with each of the OTG_FS_DIEPINTx registers for all endpoints to
generate an interrupt per IN endpoint. The IN endpoint interrupt for a specific status in the
OTG_FS_DIEPINTx register can be masked by writing to the corresponding bit in this
register. Status bits are masked by default.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:14 Reserved, must be kept at reset value.
Bit 13 NAKM: NAK interrupt mask
Bits 12:7 Reserved, must be kept at reset value.
Bit 6 INEPNEM: IN endpoint NAK effective mask
The core sets this bit to report any erratic errors.
Due to erratic errors, the OTG_FS controller goes into Suspended state and an interrupt is
generated to the application with Early suspend bit of the OTG_FS_GINTSTS register
(ESUSP bit in OTG_FS_GINTSTS). If the early suspend is asserted due to an erratic error,
the application can only perform a soft disconnect recover.
Indicates the speed at which the OTG_FS controller has come up after speed detection
through a chirp sequence.
01: Reserved
10: Reserved
11: Full speed (PHY clock is running at 48 MHz)
Others: reserved
In device mode, this bit is set as long as a Suspend condition is detected on the USB. The
core enters the Suspended state when there is no activity on the USB data lines for a period
of 3 ms. The core comes out of the suspend:
register (RWUSIG bit in OTG_FS_DCTL).
Reserved
0: Masked interrupt
1: Unmasked interrupt
0: Masked interrupt
1: Unmasked interrupt
USB on-the-go full-speed (OTG_FS)
rw
RM0090 Rev 18
9 8 7 6 5 4
Reserved
rw rw rw rw
3 2 1 0
rw rw
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