Table 196. Otg_Fs Input/Output Pins; Figure 386. Otg Full-Speed Block Diagram - ST STM32F405 Reference Manual

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OTG_FS functional description

USB clock at 48 MHz

OTG full-speed core

The USB OTG FS receives the 48 MHz ±0.25% clock from the reset and clock controller

(RCC), via an external quartz. The USB clock is used for driving the 48 MHz domain at full-

speed (12 Mbit/s) and must be enabled prior to configuring the OTG FS core.

The CPU reads and writes from/to the OTG FS core registers through the AHB peripheral

bus. It is informed of USB events through the single USB OTG interrupt line described in

Section 34.15: OTG_FS

System clock domain

Table 196. OTG_FS input/output pins

Digital input/output USB OTG D+ line

Digital input/output USB OTG D- line

Digital input

Analog input

Digital output

RM0090 Rev 18

USB on-the-go full-speed (OTG_FS)

USB OTG VBUS

USB OTG Start Of Frame (visibility)

Universal serial bus

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