ST STM32F405 Reference Manual page 1724

Revision history
Date Version
19-Feb-2013
(continued)
1724/1749
Table 315. Document revision history (continued)
FSMC:
Updated write FIFO size in
Updated Figure 434: FSMC block
Updated Section 36.5.4: NOR Flash/PSRAM controller asynchronous
Modified differences between Mode B and mode 1 in
Flash.
Modified differences between Mode C and mode 1 in
Flash - OE toggling.
Modified differences between Mode D and mode 1 in
asynchronous access with extended
4
Updated NWAIT signal in
Figure 450: Asynchronous wait during a write
configurations,
(CRAM), and Figure 453: Synchronous multiplexed write mode - PSRAM
Updated Table 195
Updated Section : SRAM/NOR-Flash chip-select control registers 1..4
(FSMC_BCR1..4).
DEBUG
Updated Figure 485: Block diagram of STM32 MCU and Cortex
level debug support.
Changes
Section 36.1: FSMC main
diagram.
address.
Figure 449: Asynchronous wait during a read
Figure 452: Synchronous multiplexed read mode - NOR, PSRAM
to Table 214.
RM0090 Rev 18
features.
Section : Mode 2/B - NOR
Section : Mode C - NOR
Section : Mode D -
access, Figure 451: Wait
®
-M4 with FPU-
RM0090
transactions.
access,
(CRAM).